JPS5839358A - Memory access control system - Google Patents

Abstract

PURPOSE:To control memory access timing externally and optionally by inputting timing information from outside of a circuit module, and forming the memory access timing signal on the basis of the input information. CONSTITUTION:When a bus confirmation signal 36 is turned on by a processor 31, a timing information signal 37 generated by a timing generating circuit 34 is inputted to a timing generation part 35 in a circuit module 30. On the basis of this input signal 37, the generation part 35 outputs an address strobe 38, a data strobe 39, an address output timing signal 40, a data output timing signal 41, and a data latch timing signal 42. A memory control circuit 33 uses the strobes 38 and 39 to generate an access signal 43 for a memory 32. Consequently, memory access timing is controlled externally and optionally, and memory access matched with the memory speed is made possible for a memory with any speed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for implementing a memory access control system that enables memory access at arbitrary memory access timing in a device having a processor and memory connected by a common bus.

In a device that has a processor and memory connected by a common bus, the processor occupies the common bus using the bus request/confirmation method, and inputs or outputs addresses and data in a time-sharing manner using the same terminal. It is known to utilize a circuit module having a direct memory access function that performs time-sharing memory access. FIG. 1 shows a memory access timing generation section using a conventional circuit module of this type. In Figure 1, 1
2 is a circuit module, 2 is a processor, 3 is a memory, 4 is a memory control circuit, and 5 is a timing generator in the circuit module l. The timing generation unit 5 is permitted to occupy the bus by the processor 2, and the bus confirmation signal 6 is set to O.
N (Active state is ON1 Inactive state is O
FF), the address strobe 9 and data strobe 10 are output to the outside of the circuit module 1 based on the clock 8 inside the circuit module 1, and the address output timing 11 used inside the circuit module 1.
, data output timing 12, and data latch timing 13. Here, the address strobe 9 and the data strobe 10 indicate to the outside the address output timing and the data input/output timing from the circuit module l, respectively, and are used for memory read or memory write to the memory 3 in the memory control circuit 4. This is the bus timing signal used to create the memory access signal 14. Further, address output timing 11 is the timing at which an address is output to the address data common terminal of the circuit module 1, and data output timing 12 is the timing at which data is output to the common terminal when writing a memo. Latch timing 13 is a timing at which data input to the common terminal at the time of memory read is latched into the circuit module.

By the way, conventionally, in order for the circuit module 1 to access memory according to the speed of the memory, for example, as shown in FIG.
A wait method is used in which the memory access timing is extended by inputting to the one-way module l.

FIG. 2 shows a time chart of conventional memory access timing using the above-mentioned wait method, in which K is an internal clock, 21 is a bus confirmation signal, 22 is an address strobe,
B is a data strobe, 24 is an address output timing, δ is a data output timing, an open data latch timing, and n is a wait signal. In FIG. 2, standard memory access timing when no wait signal is used is shown by a solid line. In the wait method, by inserting an ON state as shown by the dotted line in each wait signal, the data strobe n1 data output timing 5 and data latch timing signals are stretched by one period of the internal clock as shown by the dotted line. Furthermore, by inserting the ON state of the wait signal n for a longer time, the two-cycle split-L timing of the internal clock is extended.

In this way, by using the wait method, it is possible to extend the memory access timing, but it cannot be shortened, so it is possible to effectively take advantage of the high speed of the memory, which is faster than the standard memory access timing. The disadvantage is that it is not possible to access the memory used. However, in the F-type wait method, the address output timing and address strobe remain fixed, so the disadvantage is that the speed of the address latch in the memory control circuit 4 provided outside the circuit module is uniquely determined. have.

In order to solve these drawbacks, the present invention inputs timing information necessary for memory access from outside the circuit module and creates memory access timing based on the timing information. Explain in detail.

FIG. 3 shows an example of a memory access timing creation section to which the present invention is applied. In Figure 3, cabinet is a circuit module, 3
1 is a processor, 32 is a memo IJ1.331d memory control circuit, 34 is a timing information creation circuit, and 35 is a timing creation section. When the bus confirmation signal is turned on by the processor 31, the timing information signal 37 created by the timing information creation circuit 34 is input to the timing creation section in the circuit module cabinet. The timing creation section A creates memory access timing based on the timing information signal 37. Memory access timing includes address strobe 39 and data strobe 39 that are output to the outside of the circuit module, and address output timing 40, data output timing 41, and data latch timing 42 that are used inside the circuit module. The meanings of the signals are the same as explained in FIG. The memory control circuit 33 creates an access signal 43 for the memory 32 using the address strobe and data strobe 39 described above. The timing information signal 37 is a signal that includes timing information that is necessary to create the F memory access timing.

FIG. 4 shows an example of a time chart of memory access timing according to the present invention. In Figure 4, blade.

51,. 52 and 53 indicate a bus confirmation signal, timing information signal, address strobe, and address output timing, respectively, and 54 indicates a data strobe (when writing memory) or data latch timing (when reading memory).
shows. 55 indicates data output timing (when writing memory) or data strobe (when reading memory). By turning ON between bus confirmation signals, signals 52 and 53 are turned ON.
By switching ON and OFF the timing information signal 51, memory access timing signals 52, 53, .
Turn 54.55 ON or OFF.

First, the address strobe 52 is turned OFF by the first ON of the timing information signal 51, and the address output timing 5 is turned OFF by the next OFF of the timing information signal 51.
At the same time as turning 3 off, signal tone 55 is turned on. Furthermore, the signal 54 is turned OFF by the next ON of the timing information signal 510.
The timing information signal 510 is turned OFF, and the signal 55 is turned OFF when the timing information signal 510 is turned OFF.

As described above, in the present invention, instead of creating the memory access timing based on the timing information signal 51 shown in FIG. 4, the memory access timing is created within the circuit module based on the timing information signal input from outside the circuit module. can be controlled arbitrarily. In addition, the third
Although FIG. 4 shows the case where the timing information signal is inputted to the circuit module from one terminal, it is also possible to divide the timing information into a plurality of signals and input them from the plurality of terminals.

FIG. 5 shows an embodiment of the timing generation section in FIG. In Fig. 5, mark 61 is the bus confirmation signal (third
50 in FIG. 4) and a timing information signal (37 in FIG. 3, 51 in FIG. 4).

62, 63, 64, 65, and 66 are set-reset type flip-flops, which are reset when the bus confirmation signal port is OFF. When the bus confirmation signal ω turns ON, the flip-flop 62 is set, and thereafter, each time the timing information signal 61 turns ON and OFF, the flip-flops 63, 64, 65, and 66 are sequentially set to multiplex multiple timings. The timing of the number of sheets is separated from the timing information signal 61. Furthermore, by ANDing the outputs of the flip-flops 62, 63, 64, 65, and 66 as shown in FIG.
The memory access timing shown in 9.70 is created. Here, 67 and 68 are the address strobe (wing in Figure 3, 52 in Figure 4) and address output timing (40 in Figure 3, 53 in Figure 4), and 69 is the data strobe (when writing memory) or Data latch timing (when reading memory) (39.42 in Figure 3, 54 in Figure 4), 70 is data output timing (when writing memory) or data strobe (when reading memory) (39.42 in Figure 3, 54 in Figure 4).
41.39 in the figure and 55 in Fig. 4).

As shown in FIG. 5, if a method of sequentially separating multiple timings using flip-flops is used, even when a larger number of memory access timings are required,
By increasing the number of times the timing information signal is turned ON and OFF, and by adding the number of flip-flops for timing separation, it is possible to cope with seconds. Therefore, here we have explained time-sharing memory access control in which addresses and data are input or output by dividing them once each, but it is also possible to input or output by dividing the address and data as a whole into two or more divisions. It can also be applied to time-sharing memory access control.

As explained above, according to the present invention, since memory access timing information is provided from the outside, the memory access timing can be controlled arbitrarily from the outside, and the memory can be adapted to the speed of the memory regardless of the speed of the memory. It has the advantage of being accessible. Furthermore, since a plurality of pieces of timing information can be multiplexed and input, a single timing information input terminal can be used, which is particularly advantageous in that it is possible to eliminate pin bottlenecks in converting circuit modules into LSIs.

[Brief explanation of the drawing]

Fig. 1 shows a memory access method using a circuit module having a conventional memory access control section. Fig. 2 is a timing diagram of memory access timing according to Fig. 1.
The figure shows a memory access method using a circuit module having a memory access control section to which the present invention is applied, FIG. 4 is a timing diagram of memory access timing according to FIG. 3, and FIG. 5 shows memory access timing creation of FIG. 3. It is a figure showing one example of a part. Addition...Circuit module, 31...Processor, 32
...Memory, 33...Memory control circuit, 34...
Timing information creation circuit, ah...timing creation section. Representative Patent Attorney Makoto Suzuki (11) 1st diagram 2nd time diagram 3rd figure 1 4th diagram □ 5th time diagram

Claims (1)

[Claims] 1. It has a processor and a memory connected by a common bus, and the processor occupies the common bus using a bus request/confirmation method, and transmits addresses and data in a time-sharing manner using the same terminal. In a device using a circuit module having a direct memory access function that performs time-sharing memory access for input or output, a plurality of timing information such as address output timing and data output timing is transmitted to the circuit module from outside the circuit module. Memory access control characterized by inputting from one or more provided terminals and creating memory access timing in accordance with the timing information in the circuit module, thereby enabling memory access at arbitrary timing. method.