JPS5835602A - Programmable controller - Google Patents

Abstract

PURPOSE:To prevent a controlled system from being in danger, by stopping the control operation for the whole of the system quickly when any controller is abnormal in the programmable control system of the parallel link system. CONSTITUTION:Programmable controllers #1 and #2 are provided with user program memories PM, where user programs are stored, and output circuits OU which transmit external output signals. If an abnormality is detected in the controller #1, it is decided in the controller #1, and an abnormality signal ST is made high-level to drive a transistor TR30, and an abnormality signal line SB is made low-level, and all outputs of the circuit OU of the controller #1 itself are turned off. Meanwhile, the high level of an abnormality receiving signal E.ST is detected in the controller #2, and the abnormality is decided as YES, and all output signals of the circuit OU of the controller #2 itself are turned off.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention applies to programmable controllers, and in particular enables the construction of a parallel link type controller system in which a plurality of controllers are connected to each other via a link bus and the entire controller functions as one controller. programmable
Regarding the controller.

Conventionally, large-scale programmable
whereas I had to use a controller.
A parallel link type programmable controller system was designed to be able to handle large-scale control objects by using a plurality of relatively small programmable controllers. In other words,
Each programmable controller is provided with an input/output memory with a capacity sufficiently larger than the number of input/output terminals of its own device.

For example, if one programmable controller has 64 input/output terminals, and a maximum of four programmable controllers can be connected as a parallel link system, the input/output memory of each programmable controller is The output data area should have a capacity of at least 64 x 4 pits. When only one programmable controller is used, it operates as a normal controller with 64 input/output points, but when multiple programmable controllers are connected via a link bus, each other's user program Execution operation (Input/output data exchange means and user program synchronization execution means are provided for each programmable controller so that data in each input/output memory is exchanged synchronously. As a result, input/output status If etc. A control operation in which the machine receives the input/output status of the machine, executes each user program on each machine based on the overall input/output status, and communicates the execution results to each machine again. Therefore,
In a system in which four programmable controllers in the above example are linked, the Jw function is equivalent to controlling one system of large-scale control objects with one programmable controller with 64 x 4 input/output points. This can be achieved by having four programmable controllers share and execute the control program for this purpose.

In the case of the above-mentioned parallel link system, multiple linked programmable controllers function as one programmable controller, so even one of the linked programmable controllers may malfunction. If this occurs and normal control cannot be performed, unless the control operation of the entire system is stopped, the target device will be put into a completely unstable control state, which is extremely dangerous.

This invention was made in view of the above-mentioned conventional wm points, and its purpose is to:
To provide a programmable controller capable of immediately stopping m-operation of the entire system when an abnormality occurs in even one of a plurality of linked programmable controllers.

In order to achieve the above object, the present invention has an input/output memory with a capacity sufficiently larger than the number of input/output terminals of its own machine, and when connected to and displayed on another machine via a link bus, the user program of each machine can be transferred. In a programmable controller equipped with an input/output data exchange means and a user program synchronization execution means, data in each input/output memory is exchanged in synchronization with execution operations. , an abnormality signal@transmission means for transmitting this to other equipment, an abnormality signal reception means for receiving an abnormality signal emitted from another equipment, and an abnormality signal @ transmission means for receiving an abnormality signal emitted from another equipment, when an abnormality is detected in the own equipment and when an abnormality signal is supplied from another equipment. The present invention is characterized in that it includes an output inhibiting means for inhibiting the control output operation and setting the output state to a predetermined output state.

Embodiments of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, #1 and #2 are respectively programmable controllers according to the present invention, and two programmable controllers having the same configuration are connected by a link bus CB and an abnormal signal line S8, and the above-mentioned parallel link method is used. 1 is a diagram configuring a controller system.

Programmer controller #1. #2 is a user program memory PM in which a user program is stored as a basic configuration.
, an input circuit IU to which an external input signal is applied, an output circuit SOU to send out an external output signal, an input/output memory IM serving as a buffer memory for input/output data corresponding to the 1-input circuit IU and the output I1mou, and the above-mentioned user Each instruction in the program memory PM is executed in sequence at high speed, and the logic is executed based on the data in the input/output memory IM. an instruction execution means that performs arithmetic processing and rewrites the output data of the input/output memory fM with the processing results; and the input 1111t.
It has input updating means for writing the input data of J into a predetermined area of the input/output memory IM, and output updating means for setting the output data of the predetermined area of the input/output memory IM in the output circuit OU. When only one programmable controller is used, it operates in exactly the same way as a conventional programmable controller.

In the programmable controller according to the present invention, two programmable controllers #1. A link unit LLI connects #2 with signal lines CB and 8B, and two programmable controllers #1. In addition to being equipped with a machine number setter SL for determining the priority order when transmitting input/output data of the #2 cabinet, the capacity of the input/output memory 1M is the area equal to the number of terminals of the own input circuit IU and output circuit OU. In addition, it has an area corresponding to the number of terminals of the input circuit IU and output circuit OU of other devices. In addition, programmable controller #
1. #2 is provided with input/output data exchange means and user program synchronous execution means for exchanging data in each other's input/output memory IM in synchronization with the execution operations of each other's user programs when connected by link bus C8.

The above-mentioned instruction execution means, input update means, output update means,
The main signal processing operations of the programmable controller, such as input/output data exchange means and user program synchronization execution means, are performed by a central processing unit CPU comprised of a so-called microprocessor.

Both - #1. The addresses of the respective input/output memories fM in #2 are the same, and the input/output memories fM in FIG. As shown in the address area classification of M, area #11 corresponds to the input circuit 1u of #1 @ machine, and area #1
11 and #12 correspond to the output @lll0U of #1 machine. In particular, #11 is an area where the output data is rewritten by the user program of #1 @ machine, and area #12 is an area where the output data is rewritten by the user program of #2 @ machine. Similarly, #21 is #
This is the area corresponding to the input as r u of the 2Q machine, and #
21 and #22 are areas corresponding to the output circuit OU of the #2 machine. In particular, #21 is an area where the output data is rewritten by the #1 machine, and #22 is an area where the output data is rewritten by the #2 machine.

The input/output data exchange means mentioned above is from the input circuit tU to the area #11 of the input/output memory IM in the #1 machine.
The input data captured in #2j! The output data of area #11 of input/output memory IM rewritten in machine #1 is transferred to area #11 of machine #2N, and the area #11 of machine #2 is rewritten. Transfer the output data of #12 to #1 machine, transfer the input data read from input circuit IU #2j&- in #2 @ machine to #21 of #1 @ machine,
The output data of #21 that was rewritten on machine No. 2 was transferred to area #21 of No. 2-, and the output data of #2 that was rewritten on machine #2@
This control transfers the output data of No. 2 to area #22 in machine #1. The order of transfer of these input/output data, the order of input/output update operations in each machine, and the order of user program execution operations will be explained later.

No. 311 shows the configuration of the link unit [U] related to the link bus CD and the abnormal signal line S8. In FIG. 3, BTR is a bus transceiver/receiver that connects the link bus CB and the central processing unit CPU, through which the above-mentioned input/output data is exchanged. The abnormal signal line 9-SB consists of an open collector bus, and both lines 11.
The abnormal signal 12- is transmitted and received via this single signal 4118B. That is, the output element to which line 8B in link unit LU is connected consists of an open collector transistor 3°. When the abnormal signal from the central processing unit cPU reaches the level 5TSH and the transistor 3o is driven, the abnormal signal line 8B becomes the level 7. Inverter 31. And gate 32. A switch SWS is provided. When switch Sw is turned on, AND gate 32
The output port @ (this is the abnormal reception signal) is always at L level, and the state of the abnormal signal line SB is not taken in.

If switch sW is turned off, abnormal signal line 8B
When it reaches 7 tapes (L level), abnormal reception signal E-8
T becomes H level, and an abnormal signal is received by the central processing unit cPU.

The central processing unit CPU is located inside Soso. Abnormality diagnosis function (parity check) to detect abnormalities.

When an abnormality is detected by such an abnormality diagnosis function, the above-mentioned abnormality signal 5TI) is provided.
- level and activates the transistor 30.

Next, the two programmable controllers #1.
Processing procedures by both central processing units CPU when a parallel link type controller system is configured by #2 will be explained with reference to the flowchart of FIG. Own machine #1. When the initial processing is completed in #2, in the first step 101, the input circuit ILJ of the own machine is
The applied input data is input/output to a specified area of the memory IM (area #11 for #1 @ machine, #2 for #2 machine).
1). When this input updating operation is completed, each device notifies the other devices of the completion. Next step 1
At 02, the end of the input update operation is notified from each other device. Own machine #1. When the input update operation for both #2 is completed, the process proceeds to the next step 103 and 104, and #1-
Input data of area #11 of input/output memory IM to #2
Transfer to machine number. In the next step 105.106, #2
Input data in area #21 of input/output memory IM in machine @ is transferred to machine #1g4. As a result of the above, own machine #1, #
This means that they exchanged input data with each other in two batches.

Then each - #1. Step 107゜108 at $2
Then, the user programs stored in the respective user program memories PM are executed one cycle. Both #1
．． Step #2 is to notify each other when the execution of the user program is finished, and step 109 is to check whether each other machine has finished executing the user program.

Own machine #1. When #2 finishes executing the user program, the process proceeds to the next step 110 and 111, and the output data of areas #11 and #21 in the input/output memory PM of the #1 machine is transferred to the #2 machine. Then step 11
Proceeding to step 2,113, the output data of areas #12 and #22 in the input/output memory IM of #2@machine is transferred to #1j8 machine. Now each machine is 11. #2 exchanges the rewritten output data with each other by executing their respective user programs.

In the next step 114, the above-described abnormality diagnosis is performed, and it is determined whether or not there is an abnormality. If there is no abnormality and the condition is normal, the process proceeds to step 115 and the abnormality signal ST is set to L level, and the transistor 30 of the link unit LU is
make it inactive. In the next step 116, the reception message @
It is determined whether E-8T is at the H level, that is, whether an abnormality signal is being supplied from another device via the abnormality signal line S8. If no abnormality signal is being supplied from another device and the signal E-8T is at the positive level, the output updating operation of step 117 is performed.

In other words, in machine #1, the output data of areas #11 and #12 that is input to the input/output memory IM is transferred to the output circuit O.
Transfer to U. In machine #2, the output data of areas #21 and #22 are transferred to the output circuit OU. When the output 13- update operation of step 117 is completed, the process returns to the input update operation of step 101 again. By repeating the above operations, the two programmable controllers #1 and #2 function as a parallel link type controller system.

Here, it is assumed that an abnormality is detected in the τ#1 machine during the above operation. In that case, step 114 of #1 machine
If the result is YES, the process proceeds to step 118, where the abnormal signal ST is set to H level, the transistor 30 is driven, and the abnormal signal line SB is activated (L level). Next, the process proceeds to step 119, where all outputs of the own output circuit OU are turned off (output prohibited). And step 1 above
The process returns to the input updating operation without performing the output updating operation of step 17. As a result, no control output is generated from the output circuit OU in #1-, resulting in an output prohibition status.

On the other hand, since the abnormal signal line 8B is activated by #1@ machine, Step 1 is activated on the #2 machine side.
When step 16 is executed, it is detected that the abnormal reception signal 14-ME-8TtfiH level is reached, and the determination is YES, and the process proceeds to step 119.

That is, all the output signals of the own output circuit OU are turned off in step 119 without performing the output update operation in step 117. In this way, when an abnormality is detected in #1@ machine, not only is the control output operation of #1 @ machine prohibited, but the abnormality is immediately communicated to #2 @ machine, and #2J! Control output operations are also prohibited on the machine side.

Although the above embodiment describes an example in which a parallel link system is configured with two programmable controllers, the present invention is not limited to this.
Furthermore, it can be applied in exactly the same way to a parallel link type system with many programmable controllers. The abnormality diagnosis function of each of the programmable controllers mentioned above is not limited to the above-mentioned examples, but also includes functions for detecting abnormalities in battery voltage, abnormalities in concentration inside the circuit, etc.

As explained in detail above, according to the programmable controller according to the present invention, when a parallel link type controller system is configured by multiple units, if an abnormality is detected in each unit, the abnormality configures the system. It is possible to immediately prohibit the w-output operation of the entire system, and it is no longer possible to place the m-target in a dangerous state due to partial stoppage as in the conventional case.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a parallel link type controller system using two programmable controllers according to the present invention, and Fig. 2 shows the address area allocation status of the output memory IM of each machine in the same system. 3 is a diagram showing an example of the circuit of the link unit LLI, and FIG. 4 is a flowchart showing the processing procedure of each machine constituting the above system. CPU・・・・・・Central processing unit ■U...
・・・・・・Input a path OU・・・・・・Output circuit PM・・・・・・User program memory IM-
...... Input/output memory [U... Link unit SL...
・・・・・・Machine number setter CB・・・・・・・・・Link bus 8B・・・・・・Abnormal signal line Patent applicant Tateishi Electric Co., Ltd. 17-

Claims (1)

[Claims] (1) When the machine has an input/output memory with a capacity sufficiently larger than the number of input/output terminals of its own machine and is connected to another machine via a link bus, data in each other's input/output memory can be synchronized with the execution of each other's user programs. In a programmable controller equipped with an input/output data exchange means and a user program execution means, when an abnormality is detected by an abnormality diagnosis means inside the device, an abnormality signal transmission means for transmitting the detected abnormality to another device; an abnormal signal receiving means for receiving an abnormal signal emitted from the device; and when an abnormality is detected by the device itself or when an abnormal signal is supplied from another device, the #JIll output operation is prohibited and the output state is set to a predetermined state. A programmable controller comprising output inhibiting means.