JPS5824950B2 - semiconductor logic circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor logic circuit device, particularly a semiconductor logic circuit device having a
Logic that combines one or more unit logic sections
In a semiconductor logic circuit device manufactured based on, for example, the mask-slice design method, in which the units are arranged in a distributed manner, the wiring area in the central part of the chip surface is made larger than that in the peripheral part. The present invention relates to a semiconductor logic circuit device in which a logic unit is arranged.

Recently, semiconductor logic circuit devices manufactured based on a so-called mask-slice design method have become known in order to provide the manufactured semiconductor logic circuit devices with flexibility in use.

The mask slice design method referred to here can be considered to be based on the following concept.

That is, a unit logic section is formed by combining circuit elements such as transistors and resistors as many as one or more relatively simple logic gates or flip-flops.

A logic unit is constituted by one or more such unit logic sections.

Such logic units are distributed and arranged on the chip surface, and the remaining area is left as a wiring area.

Semiconductor logic circuit devices configured in this manner are manufactured in stock in advance, and when a necessary logic circuit is provided, the logic is configured using logic gates on the logic unit, and further necessary wiring is performed. The desired logic circuit device is completed.

However, conventionally, semiconductor logic circuit devices manufactured based on the above-mentioned mask-slice design method have a structure in which the above-mentioned logic units exist between each other, taking into consideration the possibility of configuring any logic circuit in the future. The width of the wiring area is made uniform so that the wiring area can be used equally from the perspective of each logic unit.

In other words, the logic units are distributed so that the intervals between the logic units are equal.

However, when looking at semiconductor logic circuit devices that are actually used, as will be described later with reference to Figure 1, the number of wires in the center of the chip surface is large, so it is difficult to keep the wiring area uniform as in the past. In this case, the wiring area between each logic unit must be enlarged also in the peripheral area of the chip, and the overall chip size becomes undesirably large.

The present invention aims to solve the above-mentioned problems, and the semiconductor logic circuit device of the present invention has one or more unit logic sections assembled on a chip surface to form a single logic unit. In addition to distributing and arranging the logic units, the remaining area on the chip surface where no circuit elements are present on the logic unit is used as a wiring area, and is connected to the logic unit and/or the wiring area. In a semiconductor logic circuit device having terminals, the logic units are arranged non-uniformly on a single chip so that the width of the wiring area is wider at the center of the chip surface than at the periphery of the chip surface. It is characterized by its distributed arrangement.

This will be explained below with reference to the drawings.

FIG. 1 is an explanatory diagram for explaining the distribution of the number of wires in a semiconductor logic circuit device, FIG. 2 is an embodiment of the semiconductor logic circuit device of the present invention, and FIGS. An example is shown.

In FIG. 1, 1 is a chip (or chip surface), 2 is a logic unit, 3 is an area between logic units that constitutes the wiring area or a part thereof as referred to in the present invention, and 4 is an edge of the chip. exists in

This represents an empty area constituting the wiring area or a part thereof according to the present invention.

In FIG. 1, one unit logic section directly constitutes one logic unit.

Logic units 2 are distributed on chip surface 1.

The device is then placed in a state where it is placed in use, with wiring etc. applied as necessary.

For a large number of semiconductor logic circuit devices placed in use in this way, if we investigate the number of wires that intersect one coordinate position on the It becomes a curve.

Although the shape of the curve in the frequency graph changes slightly depending on the type of unit logic section and the logical size of the unit logic section, in a semiconductor logic circuit device with a high degree of integration, the curve A or B above As shown, the wiring density in the center of the chip surface 1 is uniform.

Furthermore, the pattern of curve B is the input/output terminal PAD of the chip.
appears when the number of logic units is relatively large compared to the number of logic units.

Note that the wiring area on the chip surface 1 is generally between the logic units 2 and between the logic units 2 and 2.
It is given by the empty area 4 between the edge of the chip 1 and the edge of the chip 1.

However, the empty area on the logic unit 2 may be used for wiring between units, and the area 3 or 4 may be used for wiring within the unit as the case may be.

For this reason, the wiring area according to the present invention may be considered to include the above-mentioned areas 3 and 4 and the empty area in which no circuit element is present on the unit logic section or logic unit.

FIG. 2 shows the configuration of an embodiment of the present invention, and the reference numeral 1.
3 and 4 correspond to FIG. 1, respectively, and 5 represents a unit logic section.

In the illustrated case, when the width of the region 3 at the center of the chip surface 1 is a1 and the width of the region 3 at the periphery of the chip surface 1 is b or C, the following relationship is given in the order: a>b>c.

As a result, a wiring area corresponding to the curve A shown in FIG. 1 is secured.

FIG. 3 shows another embodiment of the present invention, in which reference numerals 1,
3, 4, and 5 correspond to FIG.

In the case shown, the width of region 3 on chip surface 1 is a >
, b > c, and the wiring area is secured to match the curve B shown in FIG.

FIG. 4 shows another embodiment of the present invention, in which reference numerals 1,
3, 4, and 5 correspond to FIG.

In the case of this embodiment, care is taken so that the unit logic parts 5 are aligned in a straight line in the transverse direction.

Of course, it goes without saying that consideration may be given to aligning them in a straight line in the longitudinal direction.

This embodiment can be considered to have an additional layer of unit logic sections 5 on the outer periphery of the structure shown in FIG. 2, so that the unit logic sections 5 are arranged in a straight line in the transverse direction.

In this case as well, in the width of region 3, a > b > c
It gives a relationship.

FIG. 5 shows still another embodiment of the present invention, and the symbols 1, 3, 4, and 5 in the figure correspond to those in FIG.

In the case shown in the figure, the width a of the region 3 at the center and the width C of the region 3 at the periphery are in two steps, with a relationship such that a>C.

That is, although the width region 3 is eliminated, there is an advantage that the unit block portions 5 are arranged in a straight line both vertically and horizontally.

FIG. 6 shows still another embodiment of the present invention, with reference numeral 1
, 2, 3, 4, and 5 correspond to FIG. 1 and FIG. 2, respectively.

In the illustrated case, four unit blocks 5 are combined to form one logic unit, but in the center -
The structure is still such that the width of the region 3 at the periphery is larger than the width of the region 3 at the periphery.

Note that even when a configuration is adopted in which one logic unit 2 includes a plurality of unit block sections 5, a logic unit is used instead of the unit block section 5 shown in FIGS. 2 to 5.
It goes without saying that a structure replacing unit 2 can be adopted.

As explained above, according to the present invention, even in a semiconductor logic circuit device based on the conventional mask-slice design method, the wiring area in the center of the chip with high wiring density is set as a dog, so that the entire chip can be It becomes possible to reduce the size.

In other words, when distributing the wiring evenly on a single chip, if the desired wiring area is taken at the center, there will be a surplus at the periphery, but in the case of the present invention, the surplus is eliminated and the overall size of the chip is reduced. can be reduced.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining the distribution of the number of wires in a semiconductor logic circuit device, FIG. 2 is an embodiment of the semiconductor logic circuit device of the present invention, and FIGS. An example is shown. In the figure, 1 is a chip (or chip surface), 2 is a logic unit, 3 is an area between logic units, 4 is an empty area on the edge of the chip, and 5 is a unit logic section.

Claims (1)

[Scope of Claims] 1. A single-shaped logic unit is used as a set of one or several unit logic parts on a chip surface, and the logic unit is distributed and arranged, and the logic - In a semiconductor logic circuit device in which the remaining area on the chip surface where no circuit element is present on the unit is used as a wiring area, and the logic unit and/or the wiring area has a connecting terminal, the width of the wiring area is as described above. The chip at the center of the chip surface. A semiconductor logic circuit device characterized in that the logic units are non-uniformly distributed on a single chip so that the logic units are distributed more uniformly than in the periphery of the surface. 2. The logic unit is a wiring located near the edge of the chip in the periphery of the chip surface. 2. The semiconductor logic circuit device according to claim 1, wherein the semiconductor logic circuit device is arranged so that the width of the region is smaller than the width of the wiring region at a position far from the edge. 3. The semiconductor logic circuit device according to claim 1 or 2, wherein all of the connection terminals are left unconnected. 4. The semiconductor logic circuit device according to claim 1 or 2, wherein in the semiconductor logic circuit device, some of the connection terminals remain in an unconnected state.