JPS58212159A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS58212159A JPS58212159A JP57095345A JP9534582A JPS58212159A JP S58212159 A JPS58212159 A JP S58212159A JP 57095345 A JP57095345 A JP 57095345A JP 9534582 A JP9534582 A JP 9534582A JP S58212159 A JPS58212159 A JP S58212159A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 239000000758 substrate Substances 0.000 claims description 10
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 238000005468 ion implantation Methods 0.000 abstract description 5
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 34
- 238000000034 method Methods 0.000 description 11
- 238000002955 isolation Methods 0.000 description 10
- 239000012535 impurity Substances 0.000 description 6
- 230000005684 electric field Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001133 acceleration Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004898 kneading Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000007873 sieving Methods 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0826—Combination of vertical complementary transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/761—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
- H01L21/82285—Complementary vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0922—Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体集積回路装置に関し、特に高速のバイポ
ーラトランジスタを含む半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a high-speed bipolar transistor.
半導体集積回路装置にはPNPトランジスタ。PNP transistors are used in semiconductor integrated circuit devices.
NPN トランジスタ等が一体化構成さねている。NPN transistors etc. are integrated.
ここで、一般にNPN)ランジスタのスイッチング速度
は高速にすることが出来る反面、PNPトランジスタは
構造が複雑であったり、横方向形成されたものは高速に
することが出来ない欠点を有する。従って、PNP )
ランジスタ、NPN)ランジスタとを含む半導体集積装
置はその両トランジスタの速度的なアンバランスが生じ
る故に全体・1゛・べ
として見た場合、回路的にも□多くの制限かぁ−・た。Generally, the switching speed of NPN transistors can be increased, but PNP transistors have a complicated structure or are formed laterally, and therefore cannot be increased in switching speed. Therefore, PNP)
Semiconductor integrated devices including transistors (NPN transistors, NPN transistors) suffer from a speed imbalance between the two transistors, so when viewed as a whole, there are many limitations in terms of circuitry.
第1図はPNP トランジスタ、NPNトランジスタを
一体化形成した従来の半導体集積回路装置を示す。FIG. 1 shows a conventional semiconductor integrated circuit device in which a PNP transistor and an NPN transistor are integrally formed.
第1図において、1はp形基板、2は高濃度n形埋込み
層、3はn形エピタキシャル層、4は予備分離拡散層を
示す。6はエピタキシャル層3表面から形成された分離
拡散層で、予備分離拡散層4と途中で接続され、活性領
域の分離を行なっている。In FIG. 1, 1 is a p-type substrate, 2 is a heavily doped n-type buried layer, 3 is an n-type epitaxial layer, and 4 is a preliminary isolation diffusion layer. Reference numeral 6 denotes an isolation diffusion layer formed from the surface of the epitaxial layer 3, which is connected to the preliminary isolation diffusion layer 4 midway to isolate the active region.
6e、6c、7bはp型拡散層である。ここで、NPN
)ランジスタ部分においては7bはベースとなるp型頭
域で、ラテラルPNP )ランジスタ部分においては6
e 、6cはそれぞれエミッタとコレクタを形成してい
る。8bはPNP )ランジスタのベース領域用のコン
タクト、9eidNPNのトランジスタのエミッタ、9
CはNPN )ランジスタのコレクタコンタクトのだめ
の高濃度n膨拡散層である。第1図で1体化形成された
、NPNPNP )ランジスタ、、において、PNPの
横型トラ・:■
ンジスタはベース巾(、、領域6eと6o間距離)が平
面的、つ1リマスクのパターン精度で定まる。6e, 6c, and 7b are p-type diffusion layers. Here, NPN
) In the transistor part, 7b is the base p-type head area, lateral PNP) In the transistor part, 6
e and 6c form an emitter and a collector, respectively. 8b is the contact for the base region of the PNP transistor, 9eid is the emitter of the NPN transistor, 9
C is a high concentration n-swelled diffusion layer that serves as the collector contact of the NPN transistor. In the NPNPNP) transistor, which is integrally formed in Fig. 1, the PNP horizontal transistor has a flat base width (distance between regions 6e and 6o) and a single remask pattern accuracy. Determined.
一般に、マスク精度はそれほど正確なものでないため、
通常短かいもので3μm程度である。従って、ベース巾
の狭いPNP)ランジスタを形成出来ない。また、NP
Nトランジスタのベース領域7bにおいては拡散によっ
て濃度傾斜がついているため、電界傾斜がベース領域で
形成されるのでキャリアの加速がなされ高速化が実現す
る。しか(〜、PNP )ランジスタのベース領域3u
エピタキシヤル層そのものであり、濃度傾斜がなく高速
化が実現されない。In general, the mask accuracy is not very accurate, so
Usually, the short length is about 3 μm. Therefore, a PNP (PNP) transistor with a narrow base width cannot be formed. Also, NP
Since the base region 7b of the N transistor has a concentration gradient due to diffusion, an electric field gradient is formed in the base region, so that carriers are accelerated and high speed is achieved. However, the base area 3u of the (~, PNP) transistor
Since it is an epitaxial layer itself, there is no concentration gradient and high speed cannot be achieved.
更に、PNPトランジスタのコレクタ領域6Cの濃度が
ベース領域3よりむしろ高く、ベース巾を縮少していっ
た場合、コレクタ、エミッタ間耐圧が急速に下がる6
以上の様に、従来のPNP )ランジスタはベースI+
]が広い、拡散プロファイルにより電界傾斜がついてい
ない、PNPトランジスタのエミッタ、コレクタが同一
濃度である等の理由により横型PNPトランジスタは縦
型NPN )ランジスタに比し著しるしく特性が劣るの
が通常で、ある。従って、第1図に示す半導体集積回路
装置においては全体としての特性が不充分なものとなっ
ていた。Furthermore, the concentration of the collector region 6C of the PNP transistor is higher than that of the base region 3, and when the base width is reduced, the withstand voltage between the collector and emitter decreases rapidly.6 As shown above, the conventional PNP transistor I+
] is wide, there is no electric field gradient due to the diffusion profile, and the emitter and collector of a PNP transistor have the same concentration, so horizontal PNP transistors usually have significantly inferior characteristics compared to vertical NPN transistors. ,be. Therefore, the semiconductor integrated circuit device shown in FIG. 1 has insufficient characteristics as a whole.
次に、これを改善した半導体集積回路装置の従来例を第
2図に示す。第2図の場合はPNP )ランジスタを縦
型形成したものである。Next, FIG. 2 shows a conventional example of a semiconductor integrated circuit device that has improved this. In the case of FIG. 2, a PNP transistor is formed vertically.
第2図において、11はp型基板、12は高濃度n型埋
込み層、13はn型エピタキシャル層、14はp型予備
分離拡散層で、15は分離拡散層である。この分離拡散
層14及び15により、活性領域を分離する。16はn
型埋込み層12上にイオン注入法等で製作されたp型頭
域で、縦型PNPのコレクタとなる領域である。17.
18はそれぞれ分離拡散層14.15の領域形成時に同
時形成されるもので、コレクタ領域12の引出し拡散層
となっている。19はベースの引き出し拡散層である。In FIG. 2, 11 is a p-type substrate, 12 is a heavily doped n-type buried layer, 13 is an n-type epitaxial layer, 14 is a p-type preliminary isolation diffusion layer, and 15 is an isolation diffusion layer. These isolation diffusion layers 14 and 15 isolate the active region. 16 is n
This is a p-type head region manufactured by ion implantation or the like on the type burying layer 12, and is a region that will become the collector of the vertical PNP. 17.
Reference numerals 18 and 18 are formed at the same time as the separation diffusion layers 14 and 15, respectively, and serve as lead-out diffusion layers for the collector region 12. 19 is a base extraction diffusion layer.
2oはp+の拡散層で分離層16と同時に形成され、縦
型PNP)ランジスタのエミyりとなる領域である。2o is a p+ diffusion layer formed at the same time as the isolation layer 16, and is a region that becomes an emitter of a vertical PNP transistor.
21は通常のNPNトランジスタのエミツタ層、22は
ベース層、23はエミッタ21と同時7に形成されたコ
レクタ番コンタクト部である。21 is an emitter layer of a normal NPN transistor, 22 is a base layer, and 23 is a collector contact portion formed at the same time as the emitter 21 .
さて、第2図でp+拡散層20、n型エピタキシャル層
13、p+型コレクタ層16によって縦型PNP )ラ
ンジスタが形成される。このPNP トランジスタは第
1図で示した横型PNPと違い、ベース1わがマスクの
寸法及び寸法精度によって決定されておらず、エピタキ
シャル層13の厚み及び、p+拡散領域16の深さに依
存しているため、拡散制御によってベース巾は狭く出来
る利点がある。しかしこの構造においても多くの欠点が
ある。Now, in FIG. 2, a vertical PNP transistor is formed by the p+ diffusion layer 20, the n-type epitaxial layer 13, and the p+-type collector layer 16. This PNP transistor is different from the lateral PNP shown in FIG. Therefore, there is an advantage that the base width can be narrowed by diffusion control. However, this structure also has many drawbacks.
捷ず第1にベース「1」であるが、これはエピタキシャ
ル層13の厚みからエミッタ20の拡散深さとp壁領域
16の上方拡散を引いたものによって決定されるので、
ベース巾の分布が非常に大きい。First of all, the base "1" is determined by the thickness of the epitaxial layer 13 minus the diffusion depth of the emitter 20 and the upward diffusion of the p-wall region 16.
The distribution of base width is very large.
それに加えるにp型拡赦層16の濃度は埋込み層12と
の濃度との加減によって決するため、子方拡散は、p型
拡散層16のドーピング量によって一義的に決まらず、
従って、ベース巾の分布は呼す−ます大きくなってしま
い、べ一東巾がパターン精度で制限されないと云うもの
のベース巾の決定制御が困難である。In addition, since the concentration of the p-type permissive layer 16 is determined by adjusting the concentration of the buried layer 12, the coterminal diffusion is not uniquely determined by the doping amount of the p-type diffusion layer 16.
Therefore, the base width distribution becomes increasingly large, and although the base width is not limited by pattern precision, it is difficult to determine and control the base width.
しかも、第1図で示したPNP )ランジスタでみられ
た欠点であるベース領域での濃度勾配及びコレクター2
の濃度が高い問題は改善されていない。Moreover, the concentration gradient in the base region and the collector 2
The problem of high concentrations of water has not been improved.
本発明は従来の欠点にかんがみなされたもので、高速の
バイポーラトランジスタを含む半導体集積回路装置を提
供することを目的とする。すなわち、本発明は横方向バ
イポーラトランジスタの低速性と縦型バイポーラトラン
ジスタの制御性を改善することによって、高速のPNP
及びNPNのバイポーラトランジスタを含む半導体集積
回路装置を提供せんとするものである。更に、本発明は
高速のバイポーラトランジスタとIL素子等のデバイス
を何ら製造工程を増力11することなく一体化形成り能
な半導体集積回路装置を提供せんとするものである。The present invention has been made in view of the conventional drawbacks, and an object of the present invention is to provide a semiconductor integrated circuit device including a high-speed bipolar transistor. That is, the present invention improves the low speed of lateral bipolar transistors and the controllability of vertical bipolar transistors, thereby realizing high-speed PNP transistors.
It is an object of the present invention to provide a semiconductor integrated circuit device including an NPN bipolar transistor. Furthermore, the present invention aims to provide a semiconductor integrated circuit device that can integrate devices such as high-speed bipolar transistors and IL elements without increasing the manufacturing process.
以下、本発明の構成を図面を用いて説明する。Hereinafter, the configuration of the present invention will be explained using the drawings.
第3図は本発明の一実施例に係る半導体集積回路11′
1
装置の構造断面図を示すも□1.□・のである。本実施
例においては縦型のPNP )ランジスタと縦型NPN
トランジスタ、高速縦型NPN)ランジスタを一体化形
成したものであり、縦型PNP )ランジスタ及び高速
縦型NPN)ランジスタの部分に改良を加えたものであ
る。第3図において、31はp型、半導体基板、32は
n型高濃度埋込領域、33は05〜1oΩ−cm程度の
n型エピタキシャル層で3〜4μmの厚さに成長される
。34はp型高濃度の予備拡散領域で、エピタキシャル
層33表面から形成されるp車高濃度拡散領域36と対
をなし、エピタキシャル層33の分離を行なっている。FIG. 3 shows a semiconductor integrated circuit 11' according to an embodiment of the present invention.
1 A cross-sectional view of the structure of the device is shown□1. □・No. In this example, a vertical PNP) transistor and a vertical NPN are used.
It is an integrated structure of a transistor and a high-speed vertical NPN) transistor, and is an improved version of the vertical PNP transistor and the high-speed vertical NPN) transistor. In FIG. 3, 31 is a p-type semiconductor substrate, 32 is an n-type high concentration buried region, and 33 is an n-type epitaxial layer of about 0.5 to 10 Ω-cm, which is grown to a thickness of 3 to 4 μm. Reference numeral 34 denotes a p-type high concentration pre-diffusion region, which forms a pair with a p-type high concentration diffusion region 36 formed from the surface of the epitaxial layer 33 to separate the epitaxial layer 33.
この分離領域34.35は酸化膜分離によ−)て行なっ
ても本発明の効果は変らない。36はp型の高濃度領域
で、埋込み領域32の内側に設置せられ、分離領域34
と同時に形成せられている1)しかし、高濃度埋込領域
36の表面濃度は、基板31上の埋込領域32が高濃度
のためにがなり下がっており、そのため上方への拡散は
拡散領域34はど高くならない。37は拡散領域35と
同時に形成されたp+拡散領域で、コレクタ抵抗の削減
のために設置せらtまたものである。Even if these isolation regions 34 and 35 are formed by oxide film isolation, the effects of the present invention will not change. 36 is a p-type high concentration region, which is installed inside the buried region 32 and is connected to the isolation region 34.
1) However, the surface concentration of the high-concentration buried region 36 is lowered due to the high concentration of the buried region 32 on the substrate 31, and therefore the upward diffusion is lower than that of the diffusion region. 34 is not very expensive. Reference numeral 37 denotes a p+ diffusion region formed at the same time as the diffusion region 35, which is also provided to reduce collector resistance.
38はnの拡散領域で、埋込領域32と接続される。3
9は本発明にかかわる主要拡散部で、低ドーズのイオン
注入法により形成され、シート抵抗値として通常のベー
ス抵抗の2000/口に比し1桁以上高い2にΩ/口〜
4にΩ/口程度のp−領域である。4oはn型ウェルで
p−領域39上に形成されPNP)ランジスタのベース
で領域41と同時形成される。42は約200Ω/口程
度に形成されるp領域でPNP )ランジスタのエミッ
タであり、NPN)ランジスタのベース領域43及び高
速NPNトランジスタのベース44と同時に形成される
。38 is an n diffusion region connected to the buried region 32; 3
9 is the main diffusion part related to the present invention, which is formed by a low-dose ion implantation method, and has a sheet resistance value of 2Ω/mm, which is more than an order of magnitude higher than the normal base resistance of 2000/mm.
4 is in the p-region of about Ω/mouth. 4o is an n-type well formed on the p- region 39 and formed simultaneously with the region 41 at the base of the PNP transistor. Reference numeral 42 denotes a p-region formed to a thickness of about 200 Ω/hole and is the emitter of the PNP transistor, and is formed simultaneously with the base region 43 of the NPN transistor and the base 44 of the high-speed NPN transistor.
45はベース領域41のコンタクト拡散領域であり、N
PNトランジスタのエミッタ領域46及び高速NPNト
ランジスタのエミッタ領域49と同時に形成される。4
7.50はそれぞれNPNトランジスタ及び高速NPN
トランジスタのコレクタ33のコンタクト領域である。45 is a contact diffusion region of the base region 41, and N
The emitter region 46 of the PN transistor and the emitter region 49 of the high speed NPN transistor are formed simultaneously. 4
7.50 are NPN transistor and high speed NPN respectively
This is the contact area of the collector 33 of the transistor.
以上の明らかなように、本実施例では領域42゜40.
39で縦型PNP トランジスタが形成され、領域46
,43.33で縦型NPN )ランジスタが形成され、
領域49,44.41.33で高速NPN )ランジス
タが形成されていることがわかる。ここで、縦型PNP
)ランジスタの特性を次に説明する。従来例で述べて
来た3つの問題、qjすなわち、ベース中については、
ベースであるn領域41の形成が、低濃度のp−領域3
9内に形成されており、その濃度の制御及び深さの制御
がp″′領域39上から打込捷れるイオン注入によって
m IM−良く定められる。すなわち、ベース中はn領
域40とp領域42の拡散のみによって決定されるので
制御性が良い。つまり、第2図の場合は3つのパラメー
タであったが本実施例では2つのパラメータでベース中
が決定される。また、n領域4oは最終的にはイオン注
入後のドライブインによ−)て決められるため、−ヒか
ら下方向に濃度勾配が′ついており、電界加速が行なわ
れる構造になっているのでキャリアの走行速度が増大し
、高速動作が可能となる。父、コレクタとなるp領域3
9の濃度i1...II(
it従来例と異なり、p−であるため、耐圧も高い。As is clear from the above, in this embodiment, the area is 42°40.
A vertical PNP transistor is formed in region 39, and region 46
, 43.33, a vertical NPN) transistor is formed,
It can be seen that high-speed NPN transistors are formed in regions 49, 44, 41, and 33. Here, vertical PNP
) The characteristics of the transistor are explained below. Regarding the three problems mentioned in the conventional example, qj, that is, in the base,
The formation of the n-region 41 which is the base is the formation of the low-concentration p-region 3.
9, whose concentration and depth are well defined by ion implantation from above the p'' region 39. That is, in the base, the n region 40 and the p region Controllability is good because it is determined only by the diffusion of Since the final concentration is determined by the drive-in after ion implantation, there is a concentration gradient downward from -A, and the structure is such that electric field acceleration occurs, so the traveling speed of carriers increases. , high-speed operation is possible.P region 3 which becomes the father and collector
9 concentration i1. .. .. II(it) Unlike the conventional example, since it is p-, the withstand voltage is also high.
次に、本実施例に係る縦型NPN トランジスタと高速
縦型NPN)ランジスタについて説明する。Next, a vertical NPN transistor and a high-speed vertical NPN transistor according to this embodiment will be explained.
−第3図からもわかるように、縦型NPN トランジ1
)HP
スタと高速縦型NPN)ランジスタに1縦型戸1トラン
ジスタと同一製造EL程で容易に一体化することができ
る。すなわち、p型エミッタ領域42゜p型ベース領域
43.p型ベース領域44を同一製造工程で、n型ベー
スコンタクト領域46.n型エミッタ領域46.n型エ
ミッタ領域49を同一製造工程で、n型ベース領域40
.n型コレクタ領域41を同一製造工程で容易に形成す
ることができる。その場合、高速縦型NPN)ランジス
タは、エミツタ領域49直下部分にn型コレクタ領域3
3よりも濃度の高いn型コレクタ領域41が選択的に形
成されている。そのため、縦型NPNトランジスタに比
べて、高速縦型NPN)ランジスタは高濃度のコレクタ
領域41を有しているので、p型ベース領域44を狭く
する。従って、狭“−′幅を形成前、ph jとが1き
6・ひは・トランジスタの高速化をはかる上で効果が大
きい。-As can be seen from Figure 3, vertical NPN transistor 1
) HP transistor and high-speed vertical NPN) transistor can be easily integrated with one vertical transistor and one EL manufactured in the same manner. That is, p-type emitter region 42.degree. p-type base region 43. In the same manufacturing process, p-type base region 44 and n-type base contact region 46. n-type emitter region 46. The n-type emitter region 49 is formed in the same manufacturing process, and the n-type base region 40 is formed in the same manufacturing process.
.. The n-type collector region 41 can be easily formed in the same manufacturing process. In that case, the high-speed vertical NPN) transistor has an n-type collector region 3 located directly below the emitter region 49.
An n-type collector region 41 having a higher concentration than that of 3 is selectively formed. Therefore, compared to a vertical NPN transistor, a high-speed vertical NPN transistor has a highly doped collector region 41, which makes the p-type base region 44 narrower. Therefore, before the narrow "-' width is formed, ph j is 1, which is very effective in increasing the speed of the transistor.
さらに高濃度のコレクタ領域41を有しているため、コ
レクタ抵抗が低下するので、高電流領域で−トランジス
タのfT(利得帯域山積)が低下するいわゆるKirk
の効果を防ぐことにもなり、この点からもfTを向−4
ニさせることができる。そして、高濃度のコレクタ領域
41の部分はエミッタ直下部分に限定すると、ベース・
コレクタ間の接合W tの増加分を少なくすることがで
きる。以上述べたように、高濃度コレクタ領域41を有
するトランジスタは、通常のkf型npn )ランジ
スタに比べて高周波特性を上げるのに著しく効果がある
。そして本実施例で述べた縦型PNP )ランジスタど
容易に一体化することができ、高速性のすぐれたNPT
4 PNP
jl=、p−1,p$のトランジスタが同時に実現さ才
する。Furthermore, since it has a collector region 41 with a high concentration, the collector resistance decreases, so in the high current region, the fT (gain band stack) of the transistor decreases.
This also prevents the effect of
can be made to If the highly concentrated collector region 41 is limited to the part directly below the emitter, the base
The increase in junction Wt between collectors can be reduced. As described above, the transistor having the highly doped collector region 41 is significantly more effective in improving high frequency characteristics than a normal KF type (NPN) transistor. The vertical PNP described in this example) can be easily integrated with transistors, etc., and has excellent high-speed performance.
4 PNP jl=, p-1, p$ transistors can be realized simultaneously.
捷だ、高濃度のn型41をベース領域44直下の全域に
わたって形成しても上に述べた効果を有することができ
る。However, even if the highly concentrated n-type 41 is formed over the entire region immediately below the base region 44, the above-mentioned effect can be obtained.
以」二の様に、本実施例に係る半導体集積回路装置は旨
耐圧、篩速、尚密度縦型、PNP)ランジス〉と通常の
縦型NPN )ランジスタと高速縦型NPNトランジス
タを一体化構成出来るので高速化ICを実現する上で効
果は極めて大きい。As described below, the semiconductor integrated circuit device according to this embodiment has a high breakdown voltage, high sieving speed, high density vertical type, PNP) transistor, normal vertical NPN) transistor, and high-speed vertical NPN transistor. This is extremely effective in realizing high-speed ICs.
次に、本実施例に係る縦型PNP )ランジスタの深さ
方向不純物分布を第4図に示す。Next, FIG. 4 shows the impurity distribution in the depth direction of the vertical PNP transistor according to this example.
同図において、埋込み領域32はたとえばA、(砒素)
のような拡散係数の小さいものを使用し、分離領域36
はボロン等を使用することにより、基板31からの上方
拡散が図示したようになる。またエミッタ領域36.ベ
ース領域4o及びコレクタ領域39は、イオンt1−人
法でそれぞれボロン。In the figure, the embedded region 32 is, for example, A, (arsenic)
Use a material with a small diffusion coefficient such as
By using boron or the like, upward diffusion from the substrate 31 occurs as shown in the figure. Also, the emitter region 36. The base region 4o and the collector region 39 are each made of boron using the ion t1 method.
リン、ボロン等を打込みその後の熱処理により形成され
る。同図であきらかなように、ベース領域4oの濃度傾
斜が大きく、ベースに電界傾斜が得られる。更に、コレ
クタ領域39がきわめて低濃度であるため、ベース領域
40の形成はその深さも、ベースへの不純物の添加覇°
と、エミッタ領域42不純物量の両者により、実質的に
定められコレクタ領域39の不純物濃度に依存すること
がないので、その制御に困難f1−はない。また、本実
施例に係る構造では、NPNトランジスタのベース領域
43がPNP )ランジスタのエミッタ領域42及び高
抵抗の抵抗領域40と共通プロセスで形成されるため、
縦型PNPトランジスタを形成するために、新たなプロ
セスとして、単にベースとなき 亨さ
るn影領域40を形成するプロセス専追脈すき亨°゛t
≠非常に簡便な構造となっている。It is formed by implanting phosphorus, boron, etc. and subsequent heat treatment. As is clear from the figure, the concentration gradient in the base region 4o is large, and an electric field gradient is obtained at the base. Furthermore, since the collector region 39 has an extremely low concentration, the formation of the base region 40 is limited by its depth and doping of impurities into the base.
Since it is substantially determined by both the amount of impurity and the amount of impurity in the emitter region 42 and does not depend on the impurity concentration in the collector region 39, there is no difficulty f1- in controlling it. Furthermore, in the structure according to this embodiment, the base region 43 of the NPN transistor is formed in a common process with the emitter region 42 of the PNP transistor and the high resistance region 40.
In order to form a vertical PNP transistor, a new process is developed that focuses on the process of forming the n-shaded region 40 without simply forming the base.
≠It has a very simple structure.
次に本発明の他の実施例について説明する。Next, other embodiments of the present invention will be described.
第6図は本発明の他の実施例を示す半導体回路装置の構
造断面図で、第3図と同一番号は同一部分を小す0
第5図に、J<す実施例のものはPNP )ランジスク
のベース領域40が拡散領域38に接続さt1/こもの
を・示す。本実施例に17・いては、縦型PNP )ラ
ンジスタのベース領域4oはn影領域33に4たがって
設置さねコレクタウオール38に接するごどく形成され
ているので抵抗値が減少することどなり、高周波時ゲ1
が改善される。FIG. 6 is a cross-sectional view of the structure of a semiconductor circuit device showing another embodiment of the present invention, in which the same numbers as in FIG. 3 denote the same parts. The base region 40 of the run disk is connected to the diffusion region 38, as shown in FIG. In this embodiment, the base region 4o of the vertical PNP transistor is formed in the n-shaded region 33 so as to be in close contact with the collector wall 38, so that the resistance value decreases. High frequency game 1
is improved.
第6図は本発明の別の実施例を軍すもので、縦型PNP
)ランジスタ、縦型NPNトランジスタ。FIG. 6 shows another embodiment of the present invention, in which a vertical PNP
) transistor, vertical NPN transistor.
12
高速縦型NPNトランジスタ、ILを一体化した一生導
体集積回路装置の構造断面図を示すものである。12 shows a structural cross-sectional view of a lifetime conductor integrated circuit device that integrates a high-speed vertical NPN transistor and an IL.
本実施例においては、第3図と同一番号は同一部分を示
し、61.62はp−領域で領域39と同一工程により
形成され同−深さに設置される。In this embodiment, the same numbers as in FIG. 3 indicate the same parts, and 61 and 62 are p-regions, which are formed by the same process as the region 39 and placed at the same depth.
53.54は領域42,43.44と同一工程により形
成されたp型頭域である。この領域61と62は図示し
たごとく重ね合わされて形成されているが、これがI2
L素子のインジェクターとなっている。領域54はIL
素子のゲート領域となっている。領域62は上向きのN
PN )ランジスタのベースとなっている。領域55は
IL素子での逆方向トランジスタのコレクタとなってい
る。本実施例に係るILは領域53.54を有するため
に、ILの横型PNPトランジスタのインジェクタ電流
が少なくなるので、充分にIL縦型NPNトランジスタ
はインジェクタ電流を吸い込むことができる。53.54 is a p-type head region formed by the same process as regions 42, 43.44. These regions 61 and 62 are formed overlapping each other as shown in the figure, and this is I2.
It is an L element injector. Area 54 is IL
This is the gate region of the device. Area 62 is an upward N
PN) It is the base of the transistor. Region 55 serves as the collector of the reverse direction transistor in the IL element. Since the IL according to this embodiment has regions 53 and 54, the injector current of the horizontal PNP transistor of the IL is reduced, so that the vertical NPN transistor of the IL can sufficiently absorb the injector current.
すなわち、本実施例におソでは特性の優れたI2Lを何
らプロセスを変更することなく一体化形成出来る効果が
ある。尚、ここで、縦型PNP、)ランジスタの特性は
第3図、第5図で示した場合と同様に高速性等を満足す
るものであることは云うまでもない。That is, this embodiment has the advantage that I2L with excellent characteristics can be integrally formed without changing the process. Here, it goes without saying that the characteristics of the vertical PNP transistor satisfy high speed and the like as in the case shown in FIGS. 3 and 5.
第7図は本発明の更に別の実施例を示す半導体集積回路
装置の構造断面図であり、第6図に示す実施例のI2L
部分の改良形である。同図において第6図と同一番号は
同一部分を示す。本実施例においてはI2Lのp−領域
52に領域66をおおう如く、n型領域66が形成され
ていることが特長である。この領域66は縦型PNP)
ランジスタのベース領域40と同一工程で形成されたも
のである。従って、本実施例においてはI2Lのp−領
域62の11]が狭くなるので、I2Lの縦型NPN)
ランジスタのhFEが増加することになる。FIG. 7 is a structural cross-sectional view of a semiconductor integrated circuit device showing still another embodiment of the present invention, and the I2L of the embodiment shown in FIG.
This is an improved version of the part. In this figure, the same numbers as in FIG. 6 indicate the same parts. The present embodiment is characterized in that an n-type region 66 is formed in the p- region 52 of I2L so as to cover the region 66. This area 66 is a vertical PNP)
It is formed in the same process as the base region 40 of the transistor. Therefore, in this embodiment, since the 11] of the p-region 62 of I2L is narrowed, the vertical NPN of I2L)
The hFE of the transistor will increase.
従来の様に縦型トランジスタのベース+1]を定める方
法が、たとえばマスク精度で決まったり、プロセスの′
3〜4の拡11々プロファイルによって決定されていた
ため、ベース巾のバラツキが太きかった。こねに対し、
以−1=述べたように本発明は実質的に領域40.42
の拡散のみでベース巾が決まり、制御性が良い。The conventional method of determining the base +1 of a vertical transistor is determined by mask accuracy, for example, or due to process
Since the base width was determined by the 3rd and 4th expansion 11 profiles, there was a wide variation in the base width. For kneading,
-1 = As stated above, the present invention substantially covers the area 40.42.
The base width is determined only by the diffusion of the base, providing good controllability.
父、本発明での縦型トランジスタのコレクタが領域39
で形成されるので、コレクタの濃度が低く、ベース長を
狭くした場合耐圧劣化をおこす欠点が生じない。更に、
本発明の縦型トランジスタはベースは領域4oで形成さ
れるので濃度傾斜があり、電界加速され高速化を実現出
来る。また、本発明は、他のNPN素子、工2L、高速
NPNトランジスタとも、同一工程で製作出来しかもこ
れ、らの素子の高速性を同時に向上させる利点を有する
O
以上、本発明は簡単な構成により高速化半導体集積回路
装置を実現出来るので工業的価値が高い。Father, the collector of the vertical transistor in the present invention is region 39
Since the collector has a low concentration and the base length is narrowed, there is no problem of breakdown voltage deterioration. Furthermore,
Since the base of the vertical transistor of the present invention is formed in the region 4o, there is a concentration gradient, and electric field acceleration can be achieved to achieve high speed. Furthermore, the present invention has the advantage that other NPN elements, 2L, and high-speed NPN transistors can be manufactured in the same process, and the high-speed performance of these elements can be simultaneously improved. It has high industrial value because it can realize high-speed semiconductor integrated circuit devices.
第1図及び第2図は従来の半導体集積回路装置の構造断
面図、第3図は縦型PNP)ランジスタ、縦型NPN
トランジスタ及び高速縦型NPN )ランジスタを一体
化した本発明の実施例に係る半導体集積回路装置の構造
断面図、第4図は第3図の縦型PNP )ランジスタの
不純物分布図、第6図は第3図における縦型PNP ト
ランジスタを改良きた本発明の他の実施例を示す構造断
面図、第6図及び第7図は第3図のものにILを一体化
した本発明に係る構造断面図を示す。
36・・・・・・p+埋込領域、39・拳Φφ・・p−
コレクタ領域、40・・拳・・・n型ベース領域、41
・・・・son型コレクタ領域、42・・・・・・P型
エミッタ領域、430・・・・p型ベース領域、44@
・・・・・p型ベース領域、53・・e・・・ILイン
ジェクタ領域、64・saw・・ILゲート領域、56
・・働・−・ILコレクタ領域、56・・・・・・n型
領域。
代理人の氏名 j[埋土 中 尾 敏 男 ほか1名第
4図
′11
ンン1=Σ ()tp)
第5図Figures 1 and 2 are structural cross-sectional views of conventional semiconductor integrated circuit devices, Figure 3 is a vertical PNP transistor, and a vertical NPN transistor.
FIG. 4 is a cross-sectional view of the structure of a semiconductor integrated circuit device according to an embodiment of the present invention that integrates a transistor and a high-speed vertical NPN) transistor, and FIG. 6 is an impurity distribution diagram of the vertical PNP transistor shown in FIG. FIG. 3 is a structural cross-sectional view showing another embodiment of the present invention in which the vertical PNP transistor is improved, and FIGS. 6 and 7 are structural cross-sectional views according to the present invention in which an IL is integrated with the vertical PNP transistor shown in FIG. shows. 36...p+embedding area, 39.Fist Φφ...p-
Collector area, 40... Fist... n-type base area, 41
...son type collector region, 42...P type emitter region, 430...p type base region, 44@
...p-type base region, 53...e...IL injector region, 64, saw...IL gate region, 56
...Working ---IL collector region, 56...n-type region. Name of agent: j [Buried soil: Toshio Nakao and one other person Figure 4'11 nn1=Σ ()tp) Figure 5
Claims (4)
された他方導電型の第1.第2.第3の領域と、前記第
1の領域表面から形成された一方導電型の低濃度箱4の
領域と、前記第4.第2の領域表面から形成された他方
導電型の第6.第6の領域と、前記第6.第6.第3の
領域表面からそれぞれ同時形成された一方導電型の第7
.第8.第9の領域と、前記第6.第8.第9の領域表
面からそれぞれ同時形成された他方導電型の第10゜第
11.第12の領域とを備え、前記第4.第5゜第7の
領域で縦型トランジスタを、前記第2.第6、第8.第
11の領域で高速縦型トランジスタを、前記第3.第9
.第12の領域で縦型トランジスタを構成したことを特
徴とする半導体集積(i11路装置。(1) First semiconductor substrates of one conductivity type formed on a semiconductor substrate of the other conductivity type and separated from each other. Second. a third region, a region of the low concentration box 4 of one conductivity type formed from the surface of the first region, and the fourth region. A sixth region of the other conductivity type formed from the surface of the second region. a sixth area; and the sixth area. 6th. A seventh conductivity type simultaneously formed from the surface of the third region.
.. 8th. a ninth region; and the sixth region. 8th. The 10th and 11th regions of the other conductivity type were simultaneously formed from the surface of the ninth region. a twelfth region; 5. The vertical transistor is connected to the seventh region in the second region. 6th, 8th. A high-speed vertical transistor is formed in the eleventh region, and a high-speed vertical transistor is formed in the third region. 9th
.. A semiconductor integrated (i11) device characterized in that a vertical transistor is configured in a twelfth region.
ていることを特徴とする特メ1−請求の範囲第1項に記
載の半導体集積回路装置。(2) The sixth region is formed directly below the eighth region.
Feature 1 - A semiconductor integrated circuit device according to claim 1.
離された他方導電型の第1.第2.第3.第4の領域と
、前記第1の領域表面から形成された一方導電型の低濃
度箱6の領域と、前記第4の領域表面から前記第6の領
域と同時形成され一方導電型の低濃度箱6.第7の領域
と、前記第5.第2の領域表面から形成された他方導電
型の第8.第9の領域と、前記第8.第9.第3.第6
.第7の領域表面からそれぞれ同時形成された一方導電
型の第10.第11.第12.第13.第14の領域と
、前記第8.第11.第12.第14の領域表面からそ
れぞれ同時形成された他方導電型の第15.第16.第
17.第18の領域とを備え、前記第1.第2.第3.
第4の領域内にそれぞれ縦型トランジスタ、高速縦型ト
ランジスタ、縦型トランジスタ、注入論理回路が構成さ
れることを特徴とする半導体集積回路装置。(3) A semiconductor substrate of one conductivity type, a first semiconductor substrate of the other conductivity type formed on the substrate and separated from each other. Second. Third. a fourth region, a region of a low concentration box 6 of one conductivity type formed from the surface of the first region, and a low concentration box 6 of one conductivity type formed from the surface of the fourth region simultaneously with the sixth region. Box 6. a seventh area; and the fifth area. The eighth conductivity type formed from the surface of the second region. a ninth region; and the eighth region. 9th. Third. 6th
.. The 10.sup.7 regions of one conductivity type were simultaneously formed from the surface of the 7th region. 11th. 12th. 13th. a fourteenth region; and the eighth region. 11th. 12th. The 15th regions of the other conductivity type were simultaneously formed from the surface of the 14th regions. 16th. 17th. an eighteenth region; Second. Third.
A semiconductor integrated circuit device characterized in that a vertical transistor, a high-speed vertical transistor, a vertical transistor, and an injection logic circuit are respectively configured in the fourth region.
領域に突出形成されていることを特徴とする特許請求の
範囲第3項に記載の半導体集積回路装置。(4) No. 13. 4. The semiconductor integrated circuit device according to claim 3, wherein the fourteenth region is formed to protrude from the third region at an opposing position.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57095345A JPS58212159A (en) | 1982-06-02 | 1982-06-02 | Semiconductor integrated circuit device |
DE8383103726T DE3361832D1 (en) | 1982-04-19 | 1983-04-18 | Semiconductor ic and method of making the same |
EP83103726A EP0093304B1 (en) | 1982-04-19 | 1983-04-18 | Semiconductor ic and method of making the same |
US07/124,423 US4826780A (en) | 1982-04-19 | 1987-11-23 | Method of making bipolar transistors |
US07/295,380 US5066602A (en) | 1982-04-19 | 1989-01-10 | Method of making semiconductor ic including polar transistors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57095345A JPS58212159A (en) | 1982-06-02 | 1982-06-02 | Semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58212159A true JPS58212159A (en) | 1983-12-09 |
JPH0315349B2 JPH0315349B2 (en) | 1991-02-28 |
Family
ID=14135086
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57095345A Granted JPS58212159A (en) | 1982-04-19 | 1982-06-02 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58212159A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61111575A (en) * | 1984-11-05 | 1986-05-29 | Sony Corp | Semiconductor device |
JPS62295450A (en) * | 1986-05-19 | 1987-12-22 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
JPH01186673A (en) * | 1988-01-14 | 1989-07-26 | Hitachi Ltd | Semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS515973A (en) * | 1974-07-04 | 1976-01-19 | Nippon Electric Co | |
JPS53134374A (en) * | 1977-04-28 | 1978-11-22 | Sony Corp | Semiconductor device |
JPS56126960A (en) * | 1980-03-11 | 1981-10-05 | Nec Corp | Manufacture of semiconductor device |
-
1982
- 1982-06-02 JP JP57095345A patent/JPS58212159A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS515973A (en) * | 1974-07-04 | 1976-01-19 | Nippon Electric Co | |
JPS53134374A (en) * | 1977-04-28 | 1978-11-22 | Sony Corp | Semiconductor device |
JPS56126960A (en) * | 1980-03-11 | 1981-10-05 | Nec Corp | Manufacture of semiconductor device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61111575A (en) * | 1984-11-05 | 1986-05-29 | Sony Corp | Semiconductor device |
JPS62295450A (en) * | 1986-05-19 | 1987-12-22 | Sanyo Electric Co Ltd | Semiconductor integrated circuit |
JPH01186673A (en) * | 1988-01-14 | 1989-07-26 | Hitachi Ltd | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPH0315349B2 (en) | 1991-02-28 |
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