JPS58191461A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enhance sharply the degree of integration of the circuit connected with MOS inverters of a large number like a ring oscillator, etc., by a method wherein the loading MOS transistor of the MOS inverter is formed stacking on the driving MOS transistor of the inverter. CONSTITUTION:Field oxide films 2 and a gate oxide film 3 are formed on a substrate 1, a polycrystalline silicon film 5 is deposited thereon, and etching is performed to form a gate electrode 51 and a drain contact electrode 52. The source region 6 and the drain region 7 of the driving MOS transistor are formed according to ion implantation. An SiO2 film 8 is stacked thereon, a polycrystalline silicon film 10 is deposited thereon, etching is performed, oxidation is performed to grow a gate oxide film 11, a gate electrode 12 is formed, and the source region 13 and the drain region 14 of the loading MOS transistor are formed according to ion implantation. An SiO2 film 15 is stacked thereon, and a ground wiring 161, the gate electrode 12 of the loading MOS transistor, and an electric power source wiring 162 to be connected to the drain region 14 are formed according to evaporation of an Al film and patterning.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device including a MOS inverter, and particularly relates to a method for manufacturing a semiconductor device including a MOS inverter, and particularly relates to a method for manufacturing a semiconductor device including a MOS inverter, and in particular, a single crystal silicon substrate and a polycrystalline silicon deposited thereon via an interlayer insulating film. The present invention relates to a method for constructing a MOS inverter by forming MOB transistors on each film.

[Technical background of the invention and its problems]

Ennomement/dissolution type (E/
A MOS inverter having an element configuration of D type or enhancement/enhancement type (E/E type) is used. For example, the circuit diagram of a ring oscillator consisting of an n-channel E/E type is shown in Figure 1. As can be seen in this circuit diagram, a large number of MOS inverters are connected in cascade, and the output signal of the final stage is transmitted to the first stage. The structure is such that it is returned to the stepped section. A plan view of a single-stage MOS inverter, which is a component of this, is roughly as shown in FIG. 2, and these are repeatedly arranged horizontally. As can be seen from this figure, it usually consists of a driver MOB transistor Qs with a relatively wide channel width WD1 and a channel length LD, and a relatively narrow channel @W5 and a load MOB transistor Qs with a channel length LL.

It is. As can be seen from this, the occupied area is
In particular, the load MO8) transistor part requires a large area. This is a big problem from the viewpoint of increasing the density of integrated circuits. However, in Figure 2,
In order to clarify the problem, I deliberately chose something that is easy to understand, but in any case, the driver and load MOS)
It is not desirable to have a large number of transistors arranged in pairs on the same plane, considering the effective use of the WJ product.

[Purpose of the invention]

In view of the above-mentioned points, the present invention provides a method for manufacturing a double conductor device that allows the degree of integration of a circuit including a MOS inverter to be dramatically improved.

[Summary of the invention]

In this invention, ■ a driver MOB transistor constituting a MOS inverter is formed on a monocrystalline silicon substrate, and ■ a load MO8 transistor is formed on a polycrystalline silicon film deposited on this through an interlayer insulating film. The basic idea is to form a In this case, ■For the MO8 transistor for the driver, use the first polycrystalline silicon film to form the drain contact (Il&) at the same time as the f-) electrode, ■For the MO8 transistor for the load, use the first polycrystalline silicon film. The polycrystalline silicon film is recrystallized by scanning irradiation with an energy beam, and this film is left on the driver MO8) transistor region and turned to contact the drain contact electrode of the driver MOS transistor. It is characterized in that the region is formed to serve as a source region.

〔Effect of the invention〕

According to this invention, MOB for load of MOS inverter
) By forming the transistor horizontally on top of the MO8) transistor, the occupied area can be reduced to
O8) The degree of integration of a circuit in which a large number of MOS inverters are connected, such as a ring oscillator, can be greatly improved by relying only on transistors. Furthermore, when a load MO8) transistor is formed in a recrystallized silicon film, its mobility μ is the same as that of a driver MO8) transistor using single crystal silicon. 5θ~6
At 0%, the shapes of the load and driver MO8) transistors can be made relatively similar or larger.

[Embodiments of the invention]

An embodiment in which the present invention is applied to a ring oscillator shown in FIG. 1 will be described below. FIGS. 3(a) to 3(f) are cross-sectional views showing the manufacturing process of the one-stage MOS inverter portion. First, as shown in Figure 3(, ), p-type (100
) Using a single crystal silicon substrate 11t-, a field oxide film 27 was formed in the element isolation region, and then an f-)at film 3 of 530× was formed in a dry oxidation atmosphere at 900°C.

After that, a hole was made in the part of the dirt oxide film 3 that protruded from the contact electrode t of the drain region, and in order to form a drain region with sufficiently low resistance, an arsenic impurity was implanted using ion implantation technology to form nWt4. . The ion implantation conditions are: the dose lid is I x 10' sea 2, and the acceleration voltage is 70
It was kV. Next, a non-doped first polycrystalline silicon film 5 is deposited on the entire surface at 600° C. using a low pressure CVD device, for example.
30001 were deposited.

This was created using photolithography and etching techniques, as shown in Figure 3 (b).
) throat (f-) electrode 51 and the drain contact electrode 5 in direct contact with the n layer 4 which becomes part of the drain region;
3 was formed. This example turning of the polycrystalline silicon 5 employs the self-line method in the so-called silicon gate technology, and the process of attaching and turning the polycrystalline silicon film 5 to the y-t oxide film 3 and the field oxide film 2. When this is reached, etching will stop. After this step, arsenic ions are implanted again.

At this time, the implantation conditions are the same as before, for example, I x 10''10at2 and 70 kV.In this way, the source region 6 and drain region 7 (integrated with the previous n+ layer 4) of the MO8 transistor for the driver are formed. Ru.

Figure 4 is a plan view of two stages in the state shown in Figure 3 (b).
FIG. 3 is a cross-sectional view taken along the line A-A' of the same. As is clear from the figure, the drain contact electrode 5 is integrated with the ff-) electrode of the next-stage driver MO8).

Next, as shown in Figure 3 (,), as a layer insulation expansion,
[Deposit #600° at 350°C. All elements in this case 11 are wrapped. After this, the gto
Then, a hole W69 is formed on the drain region 1 of the film 8 using photolithography and etching techniques. When the bottom of ζ0111# reaches the drain contact electrode jl made of polycrystalline silicon, the etching stops at V! do. Next, Figure 3 (
300% of the second polycrystalline silicon group 10 as shown in d)
01 deposit. At this time, the previous window 90 portion directly contacts the underlying polycrystalline silicon. In this part 9, the polycrystalline silicon is 60001. Then, for example, 2×1012 Irons are applied to this polycrystalline silicon film 10.
After /II2 ion implantation, this was annealed using a Radhe beam. That is, using y Alpnrede,
The rask scanning speed of the beam is 9, for example 9,8 tx/
s·C, and the width of the line was 5 to 20 μm. At this time, the substrate was set in air, and the substrate surface was maintained at a temperature of 490° C. using a heater. Further, the laser power was varied from 7 to 15 wt. Under these conditions, the polycrystalline silicon film 10 was seen to be recrystallized as a type of window 9t. In this example, it was found that a radar beam power of 7 to 15 W is best; if it is too strong, the polycrystalline silicon melts and evaporates, and if it is weaker, it hardly recrystallizes. Also, 7~15W
The second polycrystalline silicon film 10 was sufficiently recrystallized between the two, and when the film was observed by an electron beam diffraction test, Kikuchi lines were clearly visible. Furthermore, when observed with a transmission electron beam, very few twins were observed. That is, it was found that although the m2 polycrystalline silicon film 10 was not recrystallized to a complete single crystal, it was recrystallized to a sufficiently high quality silicon film. After this, as shown in FIG. 3(,), the recrystallized second polycrystalline silicon film 10 is selectively left only directly above the driver MO8) transistor, and the rest is etched away. Using a silicon gate process, the surface of the recrystallized silicon film is oxidized to grow an r-to oxide film 11, and then a third polycrystalline silicon film is used to form a dirt electrode 12.
Then, as shown in FIG. 3(f), a source region 13 and a drain region 14f were formed by ion implantation. As shown in FIG. 1- Opening, vapor deposition of an At film, and odd turning to form a wiring 1611 which becomes a ground line contacting the source region 6 of the driver MO8) transistor.
2 and the drain region 14 are formed in a wiring 168' which becomes an electric wire in contact with the drain region 14.

The characteristics of the ring oscillator thus produced are shown in FIG. 5. FIG. 0 shows the supply voltage vDD (v) and the propagation delay time per stage.

The value of the β ratio in this MO8 inverter is LLμ.

Met.

The inventors further investigated and found that the load MO8)
Mobility μ in transistor is 320txs2/V-1@
MOB for driver) Mobility μ in transistor. was 61532/V.lee. Also, the load and driver MO8) transistors have f-) oxide film thickness of #
1. They were almost the same, and their dielectric constants were also almost the same. Therefore, in order to obtain the same β ratio, the length LL of the load MO8) transistor can be halved compared to the case of only ordinary bulk silicon.

In the above embodiment, the load MO8 transistor can be constructed almost directly above the driver MO8 transistor, and does not extend beyond this area. Incidentally, in order to investigate the effect of area reduction in the present invention, we compared it with a configuration in which the same β ratio was obtained by a planar arrangement on a single crystal silicon substrate using conventional technology, that is, without using beam annealing technology, and as a result, the area was reduced by 30%.

Further, in the embodiment of the present invention, y-argon lede was used, but the same effect can be obtained by using an electron beam. However, since the electron beam has a fairly high heat absorption rate, it was necessary to scan the substrate wafer a little faster. Note that the beam annealing technique used in the embodiments of this invention is an important element for the invention, as already mentioned. Incidentally, the present inventors fabricated a negatively charged MO8) transistor in the second polycrystalline silicon film without applying beam annealing. It has become clear that such an MO8 inverter cannot provide excellent optical characteristics. That is, the present inventors used a monitor wafer, grew a thermal oxide film on it, and formed a polycrystalline silicon film@3000X thereon. The growth conditions were the same as those for the second polycrystalline silicon film used in the above example.

After that, without performing laser beam annealing, the oxidation process was performed according to the normal silicon gut process.
−) An oxide film was grown. The r-t oxide film is the same as before (5
It was 30X. Subsequently, a polycrystalline silicon film was deposited to serve as a dirt electrode material. Furthermore, arsenic was implanted into the source and drain at a dose of t I x 10''/am2.

For testing purposes, the channel length was 600 μm and the channel width W was 400 μm. The measurement results of its characteristics are shown in FIG. The drain voltage VD at this time was 5■.

From this figure, the mobility μFm is found to be 10~40ω2/v
-see. This is a very low value, and such a value cannot play a role in the inverter circuit.Also, when I calculated the drain leakage current, as shown in Figure 7, the stylus force was At 5-8V, it exhibited very soft behavior. It cannot be used under these conditions. Here, we simply assume that the electric field applied to the drain end face is due to the effect from f-) and the drain voltage, so the horizontal axis is lv, l+v.

As can be seen from the above, the use of beam annealing technology is one of the important factors in obtaining the effects of the present invention.

Further, although the above description has been made using an example of an E/E type MO8 inverter, it has been recognized that the same effect can be obtained with an E/D type MO8 inverter.

[Brief explanation of drawings]

Fig. 1 is an equivalent circuit diagram of a ring oscillator using a MOB type inverter, Fig. 2 is a plan view of a one-stage MO8 inverter constructed according to the prior art, and Figs. 3 (a) to (f). ) is 1 according to an embodiment of the present invention.
A sectional view showing the manufacturing process of the MO8 inverter part of the stage, FIG. 4 is a plan view of the two stages corresponding to the state of FIG. 3(b),
FIG. 5 is a diagram showing the characteristics of the MO8 inverter according to the present example, and FIGS. 6 and 7 are diagrams showing the characteristics of the MO8 transistor of the comparative example. DESCRIPTION OF SYMBOLS 1...p-type single crystal silicon substrate, 2...field oxide film, 3...dirt oxide film, 51...f-) electrode (first polycrystalline silicon film), 53...drain Contact electrode (first polycrystalline silicon film), σ...source region, 1...drain region, 8...CVD5 t
o2 film (interlayer insulating film), 9... window, 10... second polycrystalline silicon film, 11... r-) oxide film, 12...
・f-) Electrode, 13... Source region, 14... Drain region, 15・CVD5102J[% 161 #
J 6m...Aj wiring. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 6 Figure 6 Voo = 5V de

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device including an E/D type or E/E type MOS inverter, which comprises forming f-) electrodes and drain contacts ta made of a first polycrystalline silicon film on a single crystal silicon substrate. MO for driver with
8) A step of forming a transistor, and then covering the entire surface with an interlayer insulating film, and forming an opening on the drain region of the MO8) transistor and depositing a second polycrystalline silicon film. a step of recrystallizing the second polycrystalline silicon film by scanning irradiation with an energy beam; and a step of turning the recrystallized second polycrystalline silicon film 79 times so as to leave it on the driver MO8 transistor region. and a step of forming a load MO8) transistor in which the source region is a region in contact with the drain contact electrode of the driver MO8) transistor on the slightly turned second polycrystalline silicon film. A method for manufacturing a featured semiconductor device. (2) The drain contact electrode of the 111th driver MO8) transistor is as follows R(0MO8(:,')Z-
2. The method of manufacturing a semiconductor device according to claim 1, wherein the dirt electrode of the MoS transistor for P(D driver) is formed continuously.