JPS58196582A - Display element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a fine dot display element and a gradation display method.

A conventional image display element is shown in FIG. It is constructed by combining a liquid crystal and a MOS type FB'r array.

In FIG. 1, the unit pixel tm is formed in a semiconductor layer and is of fcMOe type F1ffiT1. These are a signal storage capacitor 2 and a liquid crystal cell 3. This basic operation will be explained.

First, when MO8IPRT is made into a P channel and a negative pulse voltage is applied as a gate signal to the gate line x1,
IMeTl is turned on, and the signal applied to the signal 17yi is charged to the capacitor 2 through the FETtT1t. If the negative pulse disappears, FET1
is turned off, and the voltage applied to the capacitor 2 VC is maintained while being discharged through the liquid crystal cell and the on-resistance of the FET, and continues to be applied to the liquid crystal. Then, from the gate signal tx1, x in, x i+1...
The entire image is displayed by sequentially scanning the lines and applying image signals corresponding to the positions to the signal lines y 1 , y i+1 . . . .

At this time, the counter electrode is a common transparent electrode attached to the entire surface of glass or the like, and 4 in FIG. 1 is a common electrode terminal. The common electrode is always kept at a certain first position. Although this relatively large-scale display device is suitable for displaying moving images including halftones, ie, for displaying television images, it is extremely unsuitable for displaying still images. This is because, as mentioned above, the signal charged in the capacitor 2 is discharged through the liquid crystal cell 3, so if the write operation is not performed constantly, the voltage on both shoulders of the capacitor will gradually drop, causing the liquid crystal to sag. The voltage changes. Therefore, even when displaying a still image, it is necessary to always perform a write operation, and power is required to keep the entire circuit running.

For example, in order to write 60 images per second on a 200×200 pixel screen, approximately 2.5 M) II is required as the maximum frequency, consuming a considerably large amount of t. Note that writing 60 images per second is the minimum value necessary to avoid flickering when driving the liquid crystal with alternating current.

Furthermore, it is necessary to flow current through the signal line to charge the capacitor, which has the disadvantage of increasing power consumption.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a display element with low power consumption that is suitable for displaying still images in fat format.

The present invention will be explained below with reference to the drawings.

In FIG. 2, one display dot is shown in the display element tube of the present invention. The switching transistors 5 and 6 formed in the semiconductor layer, the memory 7, the signal selection circuit 8, and the liquid crystal cell 9 constitute one display dot. The device is also equipped with a lock source 1o (for driving the liquid crystal with full alternating current). Here, the switching transistor 56ijMO8) is composed of a transistor. In addition, the memory self is composed of Noritsubu flops, and the high voltage level signal is 11", and the low voltage level signal is
If No. 1 is @0#, @I When the II signal is input, the ω force is set to a1' (or @0'), and the previous state is maintained until the next 10" signal is input. When a signal of '0' is input, the output is set to @0'' (or 111) and that state is maintained.Furthermore, when the input is 1m, the output of the memory self is @1' It has two input terminals: a positive input terminal 7a which is set to 111 when the input is @Om, and a negative input terminal 7b whose output is set to 111 when the input is @Om.Furthermore, the signal selection circuit 80 input [
The signal from the clock source 10 is input, and the output from the cell 7 is used as a control signal to selectively output a signal in phase with the input bias and a signal in opposite phase. The output is connected to the display dot electrode 9a. The sources of switching transistors 5 and 6 are connected to signal lines y1 and 11 having opposite polarities, respectively, and the drains are connected to positive input terminal 7a and negative input terminal 7b of the memory self, respectively. Now, the output of the clock source 10 is connected to the common electrode terminal 11, and when the output of the memory self is @I II, the input and output of the signal selection circuit 80 are in opposite phase, and when the output of the memory self is @0'', the signal is selected. The operation will be explained by taking as an example the case where the input and output of the circuit 80 are in phase. First, when a negative pulse is applied as a gate signal to the gate line x1, the switching transistor (hereinafter abbreviated as 8/Tr) 5.6 It becomes on state, and the memory self's Seijin Chikanshi 7a passes through the signal S@Tr5.61.
is input to the negative input terminal 7b, and the output of the memory self is t
It is set to @11 or 101 depending on the tii information. When the gate signal dissipates, Tr 5.6 turns off, and the memory cell continues to hold the ttiiim information of @1" or @Om until the next new 1 pulse information is input. Therefore, , all II!1i1c continue to hold the currently held image until new information is written, no matter how long Vζ is.

For the element dot whose memory cell output is 111, the input and output of the signal selection circuit 8 are in opposite phase, so the waveform of the clock source, that is, the common electrode potential, and the output of the % signal selection circuit, that is, the display dot, the electrode. Assuming that the power supply voltage is V, the waveforms are reverse phase clocks as shown in 12a and 12bK in Figure 3, respectively, and the liquid crystal 9 has an AC voltage 13a of ±V.
is applied and becomes a selected dot.

On the other hand, since the output of the memory cell is the same phase clock as 12a and 12c in FIG. 3B, no voltage is applied to the liquid crystal 9 as in 1Sb. It becomes a non-selected dot.

Therefore, it is possible to display a stationary image using very little power. Because, in the case of stationary one, the signal line 7' + 7't7'' + yt++
...and gate line x1. xL÷1・・・・・・
・If all the drive circuits are stopped and only the clock source 10 is operated, the frequency of the clock source 10 is usually about ij 50 Hsa, so for example, 200X
In the case of 200 pixels, the power consumption when displaying a still image is about 1/10,000 of that of a conventional display element. ', then the capacitor Kg1 is charged, but basically the output of the f memory cell is controlled without flowing the current tube, so it is possible to design the signal line drive circuit to have a small capacity.

Furthermore, since the clock is also applied to the common electrode side, if the power supply voltage is V, it is possible to apply 2V, that is, 2V from peak to peak, to the AC waveform tube and liquid crystal, which is comparable to the voltage applied to the liquid crystal. As a result, the power supply voltage can be reduced to half that of the conventional type, and the power consumption is reduced to 4 lj just by the effect of lowering the power supply voltage. All signals are 111
Since it is a digital signal of ゜01, the peripheral drive circuit and th
By configuring all the information processing circuits with 0MO8 VC, it is possible to significantly reduce the power consumption of the entire system. Now, the display dot explained so far is a two-tone display of @1#%g#, and cannot display halftones. Therefore, as shown in FIG. 4, a plurality of display dots are combined to form one pixel. The pixels 14 are arranged in a matrix #F-, and the pixels 14 are arranged in display dots 15a, 15b, 1 having the same structure as the display dots described above.
5c.

15 (consists of 4 pieces of l!! shown) 1! i
t).

1. , 1,6°mart, □kawa. 24, big, o
1 dot) They are twice, four times, and eight times thicker than 15a, respectively, and have a geometric progression relationship with a common ratio of 2. Also, as shown in Figure 1, the display elements must be arranged in the order of 1M from smallest to largest! ! There isn't. Gradation is displayed by a combination of these four display dots. That is, by combining the selection and non-selection of the four display dots, it is possible to display 16 gradations.

Further, the number of display dots may be any number, and if the area ratio of display dots has a series of zX, and the number of display dots is 1 (n), it is natural that z!1 gradation display is possible. .

However, it is a natural number including x and ntjO. FIG. 5 shows another example of display dot combinations, in which display dots 14a,
The area ratio of 16b, 14c, and 16d is still 1:2:4:
8, making it possible to display 16 gradations as in the example shown in FIG.

In this way, the display dots shown in Fig. 2 can be changed from those shown in Figs.
By combining a plurality of them into one pixel as shown in the figure, it is possible to simultaneously achieve halftone display and a significant reduction in power consumption. In addition, in the case of the same number of pixels, the number of display dots is four times that of the conventional type, but the single signal is flI, y1, B@TrS, or 7? :Fi1
Since the signal is input to the memory cell through two paths, Tr 8 and Tr 6, the redundancy of the verification path is doubled, so the yield as a display element does not decrease.

FIG. 6 shows a specific example of the display element of the present invention.

In other words, inverters 17 and 18 are used as 7-lip flops for memory cells, and inverters 17 and 18 are
The output terminals are connected to each other, the input of the inverter 17 is connected to 8.Tr5 as the positive input of the memory cell, the input of the inverter 18 is connected to B'hTr6 as the negative input of the memory cell, and the output of the inverter 18 is connected to the memory cell. Let it be the output of the cell. Then, as a signal selection circuit, exclusive OR (
(Hereinafter abbreviated as EOR)
9 and the output of clock source 1o as KO'R.
In addition to the other input of the circuit 19, the common electrode Kameko 1
Also connect to 1. Furthermore, the output of the BOR circuit 19 is connected to the display dot electrode 9a.

Such a structure Fi1. By using VC, when the memory cell output is set to 111, an AC voltage of ±V is applied to the liquid crystal, and when the memory cell output is set to 101, no voltage is applied to the liquid crystal. , it is possible to perform exactly the same operation as explained in FIG. Here, it is desirable to use a CMOB inverter because it reduces the power consumption of the inverter 17.18Vi.

FIG. 7 shows still another embodiment of the display element of the present invention. Two transmission gates (hereinafter abbreviated as TG) 20 and 21 are used as the signal selection circuit. The #R configuration of the memory cell by inverters 17 and 18 is as follows:
This is the same as the example in FIG. 6, but the output of the memory cell, that is, the output of the inverter 18, is connected to the n-channel side gate of TG21J and the P-channel side gate of TG21, and the input terminal of the inverter 18 is connected to the P-channel side of the inverter 18. Noble gate and n channel Y channel side gate of TG21) K connection. The outputs of the TGs 20 and 21 are connected to each other and connected to the display dot electrode 9a, and the input terminal of the TG 210 is connected to a common electrode for all the fitted dots, and is connected to the clock source 10. Further, the input terminal of the TG 20 is connected to the clock source 10 via an inverter 22, with the total attenuation dot in common.

With this configuration, when the output of the memory cell is 11", TG20 is in the on state and TG21 is in the off state, so that an AC voltage of 0 V is applied to the liquid crystal cell as shown in FIG. 3A, and the same occurs. When the output of the memory cell is @0”,
No voltage is applied to the liquid crystal cell.

The eighth factor shows still another embodiment of the display element of the present invention. TG25.24 was used as the 8.Tr.

By using TG as 8@Tr, even if the power supply voltage is lowered, the 11" and @g# signs will pass through reliably, so the redundancy of the signal path is doubled even if the power supply voltage is lowered. I can do it.

In the examples shown in FIGS. 6, 7, and 8, two KOR circuits and two circuits 7'jII'i'r() are used as signal selection circuits, but in short, the output of the memory cell is 11m. At the time of 1 and 01, it is only necessary to completely invert the phase of the alternating i waveform applied to the display dot electrode, and AN
Of course, the same operation can be achieved by the combination of D circuits and the combination v4 of 0Rpjl paths, and these also fall within the scope of the present invention. In addition, two lines of 8-Tr and signal lines are provided, but 8-Tr and two signal lines are provided.
If it were possible to fabricate semiconductor parts so that TrD defects and signal line disconnections are almost eliminated, 8.
aTr.

One signal line each is sufficient.

By using the display element of the present invention as described above, a display element with extremely low power consumption can be obtained. In other words, when displaying a still image, all peripheral circuits are stopped except for the 30Hz 8 degree clock source tube, the circuit configuration is entirely digital, and the clock tube is applied to the common electrode as well. By lowering the power supply voltage, a significant reduction in power consumption can be achieved.Also, since AC drive is possible regardless of whether it is static +1lII or dynamic ljI, display elements with excellent longevity and reliability can be obtained. It will be done.

7.Furthermore, the voltage applied to the liquid crystal is intermediate and can be either the voltage for turning it on or zero, so the visual dependence of the contrast is good, the response time is fast, and the liquid crystal Nonlinearity of transmittance with respect to voltage is also completely eliminated. Therefore, it is possible to simultaneously achieve a beautiful display using fine dots with intermediate II, low power consumption, long hemorrhoid life, and high magnification, and the present invention has great industrial value.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional display element, Fig. 2 is a circuit diagram showing a display element of the present invention, and Figs. 5 (A) and (B) show liquid crystal driving voltages in the display element of the present invention. FIG. 4 @ FIG. 5 is an explanatory diagram showing the li! of the display element of the present invention. FIG. 6 is a circuit diagram showing an actual example of the present invention, and FIG. 7 is a plan view showing an example of an embodiment of the present invention #i1! FIG. 6 is a circuit diagram showing still another practical example of the present invention. 5.6°°・Switching transistor 7...
Memory cell 8...Signal selection circuit? ...Liquid crystal cell 9a...Display dot electrode 10...Clock source 11...Common electrode electrons 12a, 12b, 12c...Clock waveform 13
a, 13b...Liquid crystal drive voltage waveform 14...
...Pixel 15a 15b 15c 15d16a, 16b
, 16c, 14d ...--t&M'<dot 1
7.18...Inverter 19...Exclusive OR 20.21, 23.24...Transmission gate 22...Inverter and above Applicant Corporation Daini Seikodai Fig. 1 ¥) 2 [21 Fig. 3 (△) Fig. 3 (ffl (B) Fig. 4 Fig. 5

Claims (2)

[Claims] (1) On a semiconductor layer formed on a transparent insulating substrate such as glass, or on a semiconductor substrate, matrix-like RC-pixels are formed, and on a transparent substrate installed on the self-defense unit through a liquid crystal. In a display element using a transparent electrode tube as a counter electrode, one of the pixels is constituted by a plurality of display dots each having a different area, and at least one bit of logical memory is stored for one of the overlapping display dots. A display element characterized in that: a circuit, and a signal selection circuit for selecting either a clock 1 or a clock 2 having a phase opposite to that of the clock 1 according to the output of the first memory path are formed in the semiconductor layer. . (2) The display element according to claim 1, wherein either the clock 1 or the clock 2 signal is applied to the transparent electrode.