JPS58195263A - Device for expanding memory address - Google Patents

Abstract

PURPOSE:To expand a memory address by setting up a parameter on a specific address in a bus and assigning a memory space having a fixed size to the specific address area in the bus. CONSTITUTION:During the execution of a program, a microprocessor 1 addresses a qualification register 4. Subsequently, the microprocessor 1 sets up a parameter 4a on the qualification register 4 by using a data bus 3c. The parameter 4a is stored in the register 4 until the succeeding access to the register 4 is started. Consequently, a memory 2 is qualified, and when the processor 1 addresses an address space in the memory 2, data in the memory 2 is accessed by the address prepared by the value of the register 4 and the address of an address bus 3a. Thus, the large quantity of data can be inputted/outputted easily by the program and the memory provided with large capacity can be connected to the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory address expansion device in a microprocessor system.

Figure 1 shows a general conventional microprocessor system. In the figure, (1) has a microphone control bus (3b) and a hitter path (3C), , when retrieving a program, etc., the address bus (
3α) Address and control signals are given via the control bus (36), so that the memory (2) outputs the data of the corresponding address to the data bus (3C). The microprocessor (II) is designed to receive this information.In addition, in order to store the results of calculations inside the processor (1) in the memory (2), the above-mentioned program must be retrieved. Data is transferred to the memory (2) via the data bus (3C) using the same procedure as the IWI.

However, the bus in conventional microprocessor systems is configured as described above.

It has the disadvantage that it is impossible to implement ROM and RAM on the address space N that can be expressed by the address bits of the microprocessor (1). Additionally, when handling data of the same number of bytes in large batches, it is necessary to calculate the address of the data storage destination before the program executes the input/output of the desired data, resulting in a loss of operating time. There was a drawback.

Therefore, the present invention was made in order to eliminate the above-mentioned defects in the conventional system, and it sets a parameter to a specific address of the bus and assigns a memory space of -9 size to the specific address of the bus. It is an object of the present invention to provide a memory address expansion device that can be allocated.

An embodiment of the present invention will be described in detail with reference to FIG. 2, in which dark parts are designated by the same reference numerals as those in FIG. 1.

In FIG. 2, (4) is a modification register provided to modify the address of memory (2), (4G) is a parameter signal set in the modification register (41), -
f 2 (5) is the address decoder, (58) is the modified memo 1 decoded by the decoder (5); it is a signal indicating completion of re-elimination, and the above parameter (4α) and the ted address path (3α)
) 7) Notes are taken with a part of the dress.

Therefore, if the microprocessor (rl) in FIG. The parameters will be stored in the modification register (4) until the next modification register (4) is accessed, and the parameters will be stored in the memory (2).
is modified and then dressed with the atlas of the modified memory to enable data to be read and output from the modified memory.

In addition, in the above-mentioned practical example, the case of targeting the data storage area has been described, but it may be applied to the program area, and the same effects as in the above-described embodiment can be obtained.

As shown above, according to the present invention, the memory is configured to be accessed with an address configured using a modifier register and a bus address, so 6.
・Large amount of data? , can be easily programmed for loading and unloading.

“.

Another effect is that it becomes possible to implement a large-capacity mesh on the bus. 1

[Brief explanation of drawings]

FIG. 1 is a square diagram showing a conventional general microprocessor system, and FIG. 2 is an Azusa IR diagram showing a memory address expansion field according to an embodiment of the present invention. (1) Two microprocessors, (21: Memory. (3α) Near address bus, (36): Control path, (3(ri): Data path, (4): Modified register, (5
) two-atreless decoder. In addition, in the figure, ]ml- sign indicates M-1 or a corresponding portion. Agent Shin Kuzuno - Figure 1 Figure 2

Claims (1)

[Claims] In a microprocessor system comprising a microprocessor and a memory that are connected via an address bus, a controller bus, and a data path to exchange data, the system is equipped with a modification register that modifies the address of the memory; A memory address expansion device characterized in that access is made using an address configured using a parameter set to a bus address and a bus address.