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JPS58182443U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS58182443U
JPS58182443U JP7929582U JP7929582U JPS58182443U JP S58182443 U JPS58182443 U JP S58182443U JP 7929582 U JP7929582 U JP 7929582U JP 7929582 U JP7929582 U JP 7929582U JP S58182443 U JPS58182443 U JP S58182443U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
polycrystalline silicon
substrate
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7929582U
Other languages
Japanese (ja)
Inventor
「あ」 敬司
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP7929582U priority Critical patent/JPS58182443U/en
Publication of JPS58182443U publication Critical patent/JPS58182443U/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Fuses (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図aおよびbは従来の多結晶シリコンフユーズの平
面図および断面図、第2図aおよびbは本考案にかか)
る多結晶シリコンフユーズの平面図および断面図である
。 図中、1は多結晶シリコン、2はPSG膜、3はシリコ
ン基板、4は5in2膜、IMは溶断部を示す。
(Fig. 1 a and b are a plan view and a cross-sectional view of a conventional polycrystalline silicon fuse, and Fig. 2 a and b are according to the present invention)
FIG. 2 is a plan view and a cross-sectional view of a polycrystalline silicon fuse. In the figure, 1 is polycrystalline silicon, 2 is a PSG film, 3 is a silicon substrate, 4 is a 5in2 film, and IM is a fused portion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 多結晶シリコンフユーズの少くとも溶断部が絶縁膜を介
して、基板とは反対の導電型領域上に設けられた構造を
有することを特徴とする半導体装置。
1. A semiconductor device having a structure in which at least a fused portion of a polycrystalline silicon fuse is provided on a conductivity type region opposite to a substrate with an insulating film interposed therebetween.
JP7929582U 1982-05-28 1982-05-28 semiconductor equipment Pending JPS58182443U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7929582U JPS58182443U (en) 1982-05-28 1982-05-28 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7929582U JPS58182443U (en) 1982-05-28 1982-05-28 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS58182443U true JPS58182443U (en) 1983-12-05

Family

ID=30088482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7929582U Pending JPS58182443U (en) 1982-05-28 1982-05-28 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS58182443U (en)

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