JPS58175372A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To improve the image resolution for a charge coupled (CCD) solid-state image pickup device which extracts the optical information of a photoelectric transducer on a semiconductor substrate, by shifting the optical diodes by 1/2 picture element size for each train and selecting and reading simultaneously two trains of signals of each diode. CONSTITUTION:The signal charges of left and right optical diodes D1-1 and D1-2 are collected to a CCD vertical shift register 2-1 via transfer gates 4-1 and 4-2 and turned into signals having no distinction from each other. Thus the diodes D1-1 and D1-2 form the same optical diode D. The register 2-1 is drien by a clock pulse generator 5, and a horizontal shift register 3' is driven by a clock pulse generator 6' respectively. A burying channel 11 is formed on a semiconductor substrate 10 for a diode D1 and the register 2-1, and a CCD electrode 8 which forms a vertical shift register doubling a transfer gate is formed via a gate oxide film 9. The electric charge of the D is sent to the channel 11 via transfer gate region 4-1 and 4-2 when the voltage of a high level is applied to the electrode 8.

Description

Detailed Description of the Invention (1) Field of Application of the Invention The present invention relates to an IT conversion element on a semiconductor substrate and a charge transfer element (Charge C) for extracting optical information from each element.
1) device, hereinafter abbreviated as CCD. ) This relates to solid-state imaging devices.

(2) Prior art solid [! The elements required an imaging board with a resolution comparable to that of the imaging electron tubes used in current television broadcasting, and for this reason, 500 elements were installed in the vertical direction.

A matrix of 800 to 1000 picture elements (photoelectric conversion elements) arranged in the horizontal direction and a scanning element to accommodate the matrix are required. Therefore, the solid-state image sensing device is manufactured using MO8 large-scale circuit technology that requires high integration, and generally uses COD or MOS transistors as constituent elements.

FIG. 1 shows the basic configuration of a CCD type solid-state image sensor characterized by a low noise f. 1 is a photoelectric conversion element made of, for example, a photodiode; 2 and 3 are a vertical CCD shift register and a horizontal shift register for taking out original signals accumulated in the photoelectric conversion element group to an output terminal 4; 5 and 6 are clock pulse generators that generate tarock pulses to drive the vertical shift register and horizontal shift register, respectively. Although a two-phase clock pulse generator is shown here, either a four-phase or three-phase clock format may be adopted. Further, numeral 7 indicates a transfer gate that sends the charges accumulated in the photodiode to the vertical shift register 2. In its current form, this device becomes a monochrome image sensor, but if a color filter is stacked on top, each party diode is provided with color information, and it becomes a color image sensor.

As is well known, solid-state imaging devices have many advantages over electron tubes, such as being small, lightweight, maintenance-free, and low power consumption, and are expected to have a promising future as the next imaging device. . However, solid-state electrons still have the problem of a small number of picture elements and low resolution (as mentioned above, current devices are made using MO8 integrated circuit technology, but even with that, the number of picture elements is 500 (vertical direction) ×
400 (horizontal direction)). Due to the configuration constraints of the vertical shift register, interlacing uses a method in which odd columns (solid arrow 7-1) are read out in the first field and even columns (pointed arrow 7-2) are read out in the second field. Because the charge accumulated in the front field is 5
There are problems caused by the interlacing method, such as 0% remaining (remaining) and color solution (low If). Therefore,
Applications: This is limited to a small number of home VTRs, cameras, etc., and in order to develop a wide range of applications that take advantage of the advantages of solid-state devices in the future, it is necessary to improve the above problems, including the following. has become an urgent issue.

(3) Purpose of the present invention The purpose of the present invention is to solve the above problems, namely
The object of the present invention is to improve the resolution f of a CD-type solid-state image pickup device by improving the device configuration without relying on MO8 integrated circuit technology.

(4) Detailed Description of the Invention A vertical CCD shift register is installed in the center of the card, that is, the vertical CCD shift register is sandwiched between the left and right sides.
1lI] By arranging a single diode, resolution can be effectively improved.

(5) Example Hereinafter, the present invention will be explained in detail using Examples.

FIG. 2 is a diagram showing the basic configuration of the CCD type solid-state image sensing device of the present invention. 1-1 and 1-2t'i vertical CCD shift registers 2-1-fl allocate bit. The exposed photodiode groups 1'-1 and 1'-2 are 1-1.
1-2 is a group of photodiodes arranged horizontally shifted by 172 pixels (D/2), and is also a vertical CCD.
It is placed across the shift register 2-2. 4-1
．． 4-2.4'-1.4'-2 are transfer gates for sending signal charges accumulated in each photodiode to each vertical shift register. Here, the signal charge of the original diode 1-1.1-2 (or 1'-1.1'-2) divided into left and right is transferred to the transfer gate 4-1.4-2 (or 4'-1
．． 4'-2) to the vertical shift register 2-1 (or 2-2) for distinction (distinction between 1-1 and 1-2).
1-1 and 1-2 (or 1'
-1 and 1'-2) are photodiodes that should be considered the same (that is, in the present invention, in the conventional example (one diode in Fig. 1 is divided into halves and placed on the left and right sides of the vertical shift register). 19, 5 is a clock pulse generator for driving the vertical shift register, and 6' is a clock pulse generator for driving the horizontal shift register 3'. Here, due to the element configuration of the present invention, one more vertical shift register is arranged per horizontal bit of a picture element than in the case of the conventional element (Fig. 1), so the number of constituent electrodes of the horizontal shift register is doubled. (In other words, the pitch dimension of the horizontal register is reduced to half that of the horizontal register of FIG. 1).

FIG. 3 is a diagram showing an example of the structure and planar layout of the image sensor of the present invention shown in FIG. 2.

Figure (a) shows the element structure showing the x-x' cross section of one pixel, and 8 is a CCD electrode (usually polycrystalline silicon is used) that also serves as the transfer gate 4 and constitutes a vertical shift register. , 9 is a gate oxide film (usually SIO is used) that electrically insulates the electrode 8 and the semiconductor substrate 10, 1-1
．． 1-2 is a photodiode, and 11 is an impurity layer (a conductive layer different from the substrate 1!) that forms the buried channel of the vertical shift register.
type and relatively low concentration of unholy atoms)
It is. When a high voltage is applied to the electrode 8, the charge of the original diode is transferred into the vertical shift register (i.e., into the channel 11) via the transfer gate region 4-1.4-2 (arrow 12-1.12). -2).

The casing is a thick insulating oxide film (usually StO is used) that separates each picture element from 13#.

FIG. 4(b) is a diagram showing an example of the planar layout of the picture element, in which 8 is a CcD11 pole (shown by a solid line) 4-1.4
-2 is a transfer gate region formed by expanding a part of the electrode 8 on the photodiode side 1, and 14 is a vertical shift register 2-1'.
1) Another CCD electrode consisting of i14 (shown as a dotted line).

If 8 is made of the second layer of polycrystalline silicon, this electrode is made of the first layer of polycrystalline silicon), and 15 indicates a channel region where charges are carried.

FIG. 4 shows the clock pulse and its timing for driving the vertical shift register in the g/l element of the present invention shown in FIG. This pulse is 11",""M"11
o'' consists of three levels, -''''1#1# level' voltage) is the state in which the transfer gate 8 is opened ('''/l/l
The state in which the diode can be fed into the vertical shift register) is shown. "M# level (intermediate voltage) is the voltage that drives the vertical shift register, and by alternately applying "1" and -o" (for example, ground voltage) to the CCD electrodes that make up the vertical shift register, the signal charge is vertically Data is sequentially transferred within the register in the horizontal register direction (downward). Here, the '1# level and the following "M level" are contained within the vertical retrace period (TIL) in any pulse, but in the first field, the 11# level of the clock pulse φ is "1" of the clock pulse φ, In the second field, the 11" level of φ is outputted earlier than the 11" level of φ1. In this way, φ1 within each field
, φ both have a "1" level, and by applying pulses whose output times are inverted for each field to the image sensor of the present invention, the signals of the original diodes of two rows one row apart for each field can be obtained. It becomes possible to read out the charges. That is, in the first field, for example, the pulse φ causes n
The original diode (1'-1, 1'-2) of the nth column is selected by the -1st column (1-1, 1-2) and φ, and the source diode (1'-1, 1'-2) of each column is sent into the vertical register. The signal charge is also applied to the first column of CCDs that constitute the vertical register (2-1, 2-2).
[Below the pole, in the second field, φ is n + 1]th (1'-1, 1'-2), φ is n + 1.
The (1-1, 1-2)th photodiode is selected and transferred under the CCD electrode of the (n+1)th column constituting the n1 vertical register (2-1, 1-1). In this way, the signals of adjacent columns arranged in the same column are transferred within each vertical register at the same time, and finally transferred to the horizontal shift register. The transfer time of the signal charge in each column to the horizontal shift register is the same, but for example, the signal charge in the n - 1st column (or the nth column) is the same as the charge in the nth column (the case or the n + 1st column). 1 for
Since it is transferred to the stage division (stage closer to output 4), output 4
In the first field, signal charges can be extracted in the order of n-1°n columns, and in the second field, in the order of n and n+1 columns). In this way, the signals in adjacent columns are displayed at the same time in the vertical register, and at the required time (
Transferring signals with a time difference determined by the driving frequency per horizontal register stage makes signal processing (separation of signals in adjacent columns) extremely simple (in other words, it is possible to read two columns at the same time). In the image pickup device of the invention, signal processing can be performed in exactly the same manner as in the conventional one-column readout type device shown in FIG.

As a result, in the image sensor of the present invention, the signals of the original diodes arranged spatially shifted by 172 pixels in the horizontal direction for each column are read out as a set of two columns, n1 horizontal and vertical. Resolution can be improved in both directions (up and down). When the inventor calculated the resolution f for an image sensor having the structure of the present invention, it was found that a resolution approximately 1.8 times higher than that of an element having a conventional structure could be obtained.

The ability to improve resolution by changing the pixel arrangement as described above while keeping the number of picture elements the same as in conventional elements is difficult to achieve with current solid-state image sensors, which have an upper limit on pixel integration due to the constraints of device manufacturing technology. It has extremely great practical value.

In the above embodiment, it has been considered that both the vertical and horizontal registers are driven by the most common two-phase clock pulse, but both the vertical and horizontal registers may be driven by three-phase clock pulses or four-phase clock pulses. The vertical register shown in FIG. 5 is driven by the same two-phase clock pulses as in FIG. 2, and the horizontal register is driven by three-phase clock pulses.

Here, by using three-phase clock pulses, the number of 11 poles in the horizontal register can be reduced to 2/3 compared to the second case, and there is an advantage that the design and manufacture of the device can be facilitated. Furthermore, by installing two rows of two-phase clock type horizontal registers as shown in FIG. 6, the signal charge from vertical register 2-1 is transferred to horizontal register 3.
The signal charges from the vertical register 2-1 (arrow 16-1) can also be transferred by the horizontal register 3-2 (arrow 16-2). In this case, the horizontal register CCD
The pitch dimension of the electrodes may be the same as that of the conventional element shown in FIG. 1, making the element fabrication easier.

In addition, although the above description has been made with reference to a monochrome image pickup device to avoid loss of generality, the configuration and operation of a color device are exactly the same as those of the above-mentioned image pickup device. - As an example, FIG. 7 shows the element configuration and color correspondence when a complementary color filter is adopted.

Although 1-1 and 1-2 or 1'-1 and 1'-2 are divided into halves, they are the same photodiode as mentioned above, so for example, the (1-1, 1-2) series For the (1'-1°1'-2) series, the front row is 1/
A yellow filter, a cyan filter, and a white filter shifted by two pixels will be assigned. As explained above using the embodiment, in the present invention, the original diode is shifted by 1/2 pixel for each column. By shifting the dimensions and reading out the signals of each diode in an interlaced manner with simultaneous selection of two columns, it is possible to improve the resolution by approximately twice. Furthermore, by changing the selection of one column to the interlace selection of all two columns, which was done in conventional CCD elements, it is possible to prevent residual images, prevent color mixture, and simplify the signal processing circuit. The practical value of the present invention is extremely high.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of a conventional CCD type solid-state sensor, FIG. 2 is a diagram showing the configuration of a CCD type ML element of the present invention, and FIG. 4 is a diagram showing the structure and planar layout of the image sensor of the invention; FIG. 4 is a diagram showing a pulse e time chart for driving the image sensor of the invention shown in FIG. 2; FIGS. 5 and 6 is horizontal CC
A diagram showing an embodiment in which the configuration of the D shift register is different from that in FIG. 2, and FIG. 7 is a diagram showing the configuration of a color CCD type image sensor of the present invention in which color fill is fully laminated. 1... Original diode, 1-1.1-2... Photodiode, 1'-1, 1'-2... Original diode, 2.2
-1.2-2...Vertical CCD shift register, 4-1
．． 4-2.4'-1, 4'-2...transfer gate, 3
．． 3'・τ・Horizontal CCD shift register, 5.6'...
・Clock pulse generator, 8...C0Dt pole, 9...
・Figure 1 Figure 2 Figure YJ3 Figure 1 Graduation ζ Y 4 Figure To---￥JI Field---Kato% z 7
4-old% 5'7

Claims (1)

[Claims] 1. A group of photoelectric conversion elements provided on a semiconductor substrate to convert optical information into electrical signals and extract them, and a vertical CCD shift register and horizontal CCD shift register to sequentially transfer the electrical signals in the vertical and horizontal directions. In a solid-state image sensor equipped with a resistor. The vertical COD shift register is self-aligned between the photoelectric conversion element groups in each column, and the electric signal of each photoelectric conversion element in the photoelectric conversion element group in each column is separated to the left or right for each element. A solid-state image sensor characterized by being taken out to a vertical CCD shift register.