[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS5816557A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5816557A
JPS5816557A JP56115573A JP11557381A JPS5816557A JP S5816557 A JPS5816557 A JP S5816557A JP 56115573 A JP56115573 A JP 56115573A JP 11557381 A JP11557381 A JP 11557381A JP S5816557 A JPS5816557 A JP S5816557A
Authority
JP
Japan
Prior art keywords
package
semiconductor
substrates
circuits
mirror
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56115573A
Other languages
Japanese (ja)
Inventor
Makoto Morikawa
森川 信
Kanji Iwase
岩瀬 寛治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56115573A priority Critical patent/JPS5816557A/en
Publication of JPS5816557A publication Critical patent/JPS5816557A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074Stacked arrangements of non-apertured devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/1627Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To double the function of a semiconductor device by a method wherein two circuits mirror symmetric with each other are respectively incorporated into two semiconductor substrates and the substrates are installed in a package with their rear sides facing to each other. CONSTITUTION:Two semiconductor substrate 3a and 3b are respectively provided with circuits that are same in function and mirror symmetric with each other. The two substrates are installed on the both surfaces of a base ribbon island 5 so that the sides not provided with circuits may face each other mirror symmetry-wise. The semiconductor substrates 3a and 3b sandwiching the island 5 are housed in the cavity 8 of a package 9, and a lead 4 is bonded to pads, which results in the accomodation of two semiconductor substrates of the same function in a single package.

Description

【発明の詳細な説明】 本発明は半導体装置に係り、特に、半導体基板に形成す
る回路の形状と、その基板の取り付は位置に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular relates to the shape of a circuit formed on a semiconductor substrate and the position of mounting the substrate.

従来の半導体装置における半導体基板のパッケージへの
取り付は例を、プラスチックパッケージについて第1W
i■に、セラミックパッケージについて第1図0に示す
。従来は、パッケージ内の半導体基板取り付は面の1主
面側(2a)のみが半導体基板取り付けのために使われ
、その裏面側(2b)は半導体装置としての機能に大き
な寄与はしていなかった。
For the mounting of a semiconductor substrate on a package in a conventional semiconductor device, for example, the first W.
A ceramic package is shown in FIG. Conventionally, only one main surface (2a) of the surface was used for mounting a semiconductor substrate inside a package, and the back surface (2b) did not make a significant contribution to the function of the semiconductor device. Ta.

これに対して本発明は、半導体基板(3&)と鏡面対称
となる様な回路を作り込んだ半導体基板(3b)を、半
導体基板(3m)に対して背面対向となる様にパッケー
ジ内に装着する事により、パッケージの大きさを変える
事なく、容易に、半導体装置の機能を2倍にする事が出
来る。
On the other hand, in the present invention, a semiconductor substrate (3b) on which a circuit that is mirror-symmetrical to the semiconductor substrate (3&) is built is mounted in a package so that the back side faces the semiconductor substrate (3m). By doing so, the functionality of the semiconductor device can be easily doubled without changing the size of the package.

本発明を実施例により説明する。The present invention will be explained by examples.

第2図(2)及び第2[@が本発明の一実施例の半導体
装置であり、第2図■はプラスチックパッケージに5J
I2図0は七うセックパッケージにおいて実施した例を
示している。又、第3図■は互いに鏡面対称となる回路
を有する半導体基鈑の一例であり、第3図0はtIIi
3図に)の半導体基板を背面対向となる様に装着する例
を示している。
Figure 2 (2) and Figure 2 [@ are semiconductor devices according to one embodiment of the present invention, Figure 2 (■) is a plastic package with 5J
I2 Figure 0 shows an example implemented in the Seven Usec Package. Also, FIG. 3 (■) is an example of a semiconductor board having circuits that are mirror-symmetrical to each other, and FIG.
Figure 3 shows an example in which the semiconductor substrates shown in Figure 3) are mounted so that their backs are facing each other.

1)プラスチックパッケージに適用した場合の実施例 反転マスクを用いて、第3g(ト)に示す様に、半導体
基板(3a)と鏡面対称となる様な回路を有する半導体
基板(3b)を作り、2枚の半導体基板(3a、3b)
を第2図(2)の様にベースリボンアイランド部の両主
面に装着する。装着された2枚の基板は、第3[@に示
す様に、互いに鏡面対称である為、同一機能を有するポ
ンディングパッドは互いのパッドの真裏に位置する。そ
こで、それらのパッドを同一リードにボンディングする
1) Example of application to plastic package Using an inverted mask, as shown in 3g (g), a semiconductor substrate (3b) having a circuit mirror-symmetrical to that of the semiconductor substrate (3a) is made, Two semiconductor substrates (3a, 3b)
are attached to both main surfaces of the base ribbon island section as shown in Fig. 2 (2). Since the two mounted boards are mirror-symmetrical to each other as shown in the third [@], the bonding pads having the same function are located directly behind each other. Therefore, those pads are bonded to the same lead.

但し、基板(3m、3b)を選択する信号が入力される
パッドは別々のリードにポンディングする。
However, the pads to which signals for selecting the substrates (3m, 3b) are input are connected to separate leads.

この様にして、同一パッケージ内に同一機能を有する2
枚の基板を、それぞれを選択出来る状態で装着する事が
出来る。
In this way, two devices with the same functionality in the same package
It is possible to install two boards in a state where each can be selected.

2)セラミックパッケージに適用した場合の実施例 互いに鏡面対称な回路を作り込んだ2枚の半導体基板(
3m、3b)を、第2図0の様に、パッケージの両主面
(2m、2b)にキャビティを有するパッケージに背面
対向となる様に固着する。
2) Example of application to ceramic package Two semiconductor substrates (with mirror-symmetrical circuits built into them)
3m, 3b) are fixed to a package having cavities on both main surfaces (2m, 2b) of the package so as to face each other from the back as shown in FIG. 20.

以下プラスチックパッケージの場合と48にリードとパ
ッドをボンディングして、同一パッケージ内に同一機能
を有する2枚の半導体基板を、それぞれを選択出来る状
態で装着する事が出来る。
In the case of a plastic package, by bonding leads and pads to 48, two semiconductor substrates having the same function can be mounted in the same package in a state where each can be selected.

次に、本発明を実施する事によって得られる機能向上の
例を示す。
Next, examples of functional improvements obtained by implementing the present invention will be shown.

3)実装密度を上げる例 本発明をICメモリー等の記憶素子に適用すれば、同一
パッケージ内に同一機能を有する2枚の半導体基板を、
それぞtを選択して使用出来る状態で装着出来る為、従
来の2倍の記憶素子を実装する事が可能となり、容易に
記憶容量を2倍にする事が出来る。
3) Example of increasing packaging density If the present invention is applied to a memory element such as an IC memory, two semiconductor substrates having the same function can be placed in the same package.
Since each t can be selected and installed in a usable state, it is possible to mount twice as many memory elements as in the past, and the memory capacity can be easily doubled.

4)信頼性を向上させる例 マイコン等の論理素子に本発明を適用して、同一パッケ
ージ内に同一機能を有する2枚の半導体基板をそれぞれ
を選択して使用出来る状態で装着し、通常、は一方の半
導体基板のみを選択して使用し、その半導体基板に機#
jA障害が生じた時、もう一方の半導体基板に切り換え
て使用すれば、従来02倍の信頼度を得る事が出来る。
4) Example of improving reliability By applying the present invention to logic elements such as microcomputers, two semiconductor substrates having the same function are mounted in the same package so that each can be selectively used. Select and use only one semiconductor substrate, and
By switching to the other semiconductor substrate when a jA failure occurs, it is possible to obtain twice the reliability compared to the conventional semiconductor substrate.

【図面の簡単な説明】[Brief explanation of the drawing]

第IWJ^及び第1図0は半導体基板をパッケージの1
主面側にのみ装着した従来の半導体装置を示す断面図で
ある。#12[^及び第2図0は互いに鏡面対称な回路
を有する2枚の半導体基鈑をパッケージの両生面側に背
面対向とな4様に固着した、本発明の実施例の半導体装
置を示す断面図である。なお% 第1tli、 mzm
とも、(2)はプラスチックパッケージの場合を、@は
セラミックパッケージの場合を示している。第3図に)
は、互いに鏡面対称となる回路を有する半導体基板の正
面図であり、第3図0は縞3w1(2)で示した半導体
基板をペースリボン−アイランド部へ背面対向きなる様
に実装する際を示す斜視図である。 なお、図において、1・・・ポンディングワイヤ、2a
・・・パッケージの1主面、2b・・・パッケージの反
対側l主面、3・・・半導体基板、4・・・リード、5
・・・ペースリボン・アイランド部、6・・・プラスチ
ックパッケージ、7・・・キャップ、8・・・キャビテ
ィ。 9・・・セラミックパッケージを示す。
Part IWJ^ and Fig. 1
FIG. 2 is a cross-sectional view showing a conventional semiconductor device mounted only on the main surface side. #12 [^ and Figure 2 0 show a semiconductor device according to an embodiment of the present invention, in which two semiconductor substrates having mutually mirror-symmetrical circuits are fixed to the bidirectional side of the package in four ways with their backs facing each other. FIG. Note that % 1st tli, mzm
In both cases, (2) indicates the case of a plastic package, and @ indicates the case of a ceramic package. (see Figure 3)
3 is a front view of a semiconductor substrate having circuits mirror-symmetrical to each other, and FIG. FIG. In addition, in the figure, 1... bonding wire, 2a
... 1 main surface of the package, 2b... Opposite l main surface of the package, 3... Semiconductor substrate, 4... Lead, 5
... Pace ribbon island part, 6... Plastic package, 7... Cap, 8... Cavity. 9... Indicates a ceramic package.

Claims (1)

【特許請求の範囲】[Claims] 互いに鏡面対称な回路を作り込んだ、同一機能を有する
2枚の半導体基板を、回路が作り込まれない面が互いに
向かい合う様に、かつ%回路が作り込まれた面が互いに
ほぼ鏡面対称となる様にパッケージに装着する事を特徴
とする半導体装置。
Two semiconductor substrates with the same function, on which mirror-symmetrical circuits are built, are placed so that the sides on which no circuits are built face each other, and the sides on which circuits are built are almost mirror-symmetrical to each other. A semiconductor device characterized by being attached to a package in a similar manner.
JP56115573A 1981-07-23 1981-07-23 Semiconductor device Pending JPS5816557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56115573A JPS5816557A (en) 1981-07-23 1981-07-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56115573A JPS5816557A (en) 1981-07-23 1981-07-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5816557A true JPS5816557A (en) 1983-01-31

Family

ID=14665906

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56115573A Pending JPS5816557A (en) 1981-07-23 1981-07-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5816557A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026155A1 (en) * 1999-10-01 2001-04-12 Seiko Epson Corporation Semiconductor device, method and device for producing the same, circuit board, and electronic equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001026155A1 (en) * 1999-10-01 2001-04-12 Seiko Epson Corporation Semiconductor device, method and device for producing the same, circuit board, and electronic equipment
US6489687B1 (en) 1999-10-01 2002-12-03 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, manufacturing device, circuit board, and electronic equipment

Similar Documents

Publication Publication Date Title
KR20010023575A (en) Electrical interface to integrated device having high density i/o count
JPS5816557A (en) Semiconductor device
JPH0786526A (en) Memory device
JPS63136657A (en) Both-side mounting electronic circuit device
JPH06177322A (en) Memory element
JPH05121632A (en) Semiconductor device
JPS59100550A (en) Semiconductor device
JPS62131555A (en) Semiconductor integrated circuit device
JP2661115B2 (en) IC card
KR960019683A (en) Semiconductor devices
JPH0287661A (en) Semiconductor storage device
JP2522182B2 (en) Semiconductor device
JPH0349255A (en) Sealing of semiconductor integrated circuit
JPH04144161A (en) Semiconductor integrated circuit device
JPH0629422A (en) Hybrid integrated circuit device
KR960004090B1 (en) Semiconductor package
JPH0273662A (en) Semiconductor device
JPH03274754A (en) Semiconductor integrated circuit device
JPH05218292A (en) Hybrid integrated circuit device
JPH04262591A (en) Mounting system for integrated circuit
KR19980058604A (en) Expandable semiconductor package
JPH01114061A (en) Semiconductor package
JPH0242755A (en) Package of semiconductor integrated circuit
KR200161172Y1 (en) Semiconductor chip
KR940010292A (en) Semiconductor package