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JPS58164229A - Treatment of semiconductor substrate - Google Patents

Treatment of semiconductor substrate

Info

Publication number
JPS58164229A
JPS58164229A JP4801482A JP4801482A JPS58164229A JP S58164229 A JPS58164229 A JP S58164229A JP 4801482 A JP4801482 A JP 4801482A JP 4801482 A JP4801482 A JP 4801482A JP S58164229 A JPS58164229 A JP S58164229A
Authority
JP
Japan
Prior art keywords
hydrazine
defect
heat treatment
semiconductor substrate
gas
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4801482A
Other languages
Japanese (ja)
Other versions
JPH0568099B2 (en
Inventor
Takanori Hayafuji
早藤 貴範
Sachiko Nakazawa
中沢 幸子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP4801482A priority Critical patent/JPS58164229A/en
Publication of JPS58164229A publication Critical patent/JPS58164229A/en
Publication of JPH0568099B2 publication Critical patent/JPH0568099B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To remove rapidly a crystal defect, mainly a stacking defect and a generating nucleus thereof by a method wherein a heat treatment is performed to a semiconductor substrate in an inactive gas atmosphere or a plasma atmosphere containing NH3 and a hydrazine group or NH3 or hydrazine. CONSTITUTION:When the heat treatment is to be performed to the semiconductor substrate to remove the stacking defect, the Si crystal substrate is treated in the inactive gas atmosphere or the plasma atmosphere containing NH3 and hydrazine group or NH3 or the kind of hydrazine. At this time, a hydrazine salt of N2H4, N2H4.HCl, etc., is used, and as inactive gas containing NH3 and/or the kind of hydrazine, N2 gas or Ar gas is used. Moreover the treatment temperature is set at 1,150-1,200 deg.C, and length of the defect is reduced in a short nitriding time. Accordingly removement of the generating nucleus of the defect is attained without generating roughness and contamination of the surface.

Description

【発明の詳細な説明】 この発明は、半導体基1[4611法に関するものであ
り、IK*mには、譬に貴画粗のないゃ導体基板処II
法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the semiconductor substrate 1 [4611 method, and IK*m includes, for example, the conductor substrate processing II.
It is about law.

た2えばシリコン結晶の場金、ccnなとのイメージセ
ンサ−において、その基板として4111m8れる結晶
の積層欠陥が画像欠陥となるために1その積層欠陥を除
去するために莫大な研究がな専れて會た。たとえば、結
晶表imz<E存在する結晶欠陥または結晶欠陥の発生
核を、窒素ガス、アルゴンガスなどの不m性ガス中にお
いて熱部層する仁と番こより除去できることは知られて
いた。すなわち1シ啼プン蒙晶を高温の窒素ガス、アル
ゴンガス、水素ガス中でアニールする方法は実用化され
ている。結晶欠陥や積層欠陥の除去は、高温部層はど早
(、かつ、N!ガス中での処履が最も早くで奢る。最近
ては%N2ガス中KHCjfiimして積層欠陥の除去
管より早くする方法がI1県?!Eれている。
For example, in an image sensor such as a silicon crystal substrate (CCN), stacking faults in the 4111 m8 crystal that serves as the substrate cause image defects.1 A huge amount of research has been devoted to removing the stacking faults. We met. For example, it has been known that crystal defects existing on the crystal surface imz<E or the generation nuclei of crystal defects can be removed from a hot layer in an inert gas such as nitrogen gas or argon gas. In other words, a method of annealing a single piece of mengo crystal in high-temperature nitrogen gas, argon gas, or hydrogen gas has been put into practical use. Crystal defects and stacking faults can be removed quickly in high-temperature layers (and in N! gas. Recently, KHCJFIIM in %N2 gas has been used to remove stacking faults faster than in a tube). Is there a way to do this in I1 prefecture?!E.

しかしながら、N、、アルゴン、水嵩ガスまたはHcj
を添加した馬ガス中での高温地層は、シリコン*WJK
、@(インホ毫ジエニイーテイ)を生じさせるJ[因に
もなっている。また、110(1以上のN!ガス雰■気
中7の熟msは、すでに存在している積層欠陥モ蓼1I
Ia専甘消滅専せる効果はあるけれども、それ以上に多
くの積層欠陥の発生核を新たK[威するCとも知られて
いる。
However, N, argon, water bulk gas or Hcj
The high-temperature stratum in horse gas added with silicon*WJK
, is also the cause of J [which causes @ (inho ka ji enie tei). In addition, 110 (more than 1 N!) 7 ms in the gas atmosphere is due to the already existing stacking fault model 1I
Although it has the effect of exclusively annihilating Ia, it creates new K (also known as C) that creates more stacking fault nuclei.

この発−は、前述した如會鳥温熱部層による結晶表面の
観なもびに積層欠陥の発生核6形成というll来技術の
欠点flc譬する七ともに%質未決より早く#^欠陥、
fLに積層欠陥零よびその発生核を除去する1鍮f提供
するものである。
This phenomenon is caused by the formation of stacking fault generation nuclei 6 when observing the crystal surface using the aforementioned heating layer.
This is to provide a layer f for removing stacking faults and their generated nuclei in fL.

この発明の方法は、シリコン結晶からなる半導体基板を
NHs、ヒドラジン類またはNHlもしくはヒドラジン
類を含む不S*ガスの雰囲気またはプラズマ111気中
で熱鶏履をすることからなっている・ この発@1係る方法に使MIREれるヒドラジン類とし
ては、N2H4s N2H4”にノなどのヒドラジン塩
などが挙げられる。また、 1@(、および/またはヒ
ドラジン類を含有する不活性ガスとしてはs N2、ア
ルゴンガスなどが便188れる。
The method of this invention consists of heating a semiconductor substrate made of silicon crystal in an atmosphere of NHs, hydrazine, or a non-S* gas containing NHl or hydrazine, or in plasma 111. Examples of hydrazines used in the method related to 1 include hydrazine salts such as N2H4s, N2H4'', etc. 1@(, and/or inert gases containing hydrazines include s N2, argon gas, etc. Etc. 188 times.

この発明に係る方t&管次のようにして検討した。The method according to this invention was studied as follows.

まず、シリコン結晶を、乾燥0!中にて1100Cで1
6w#間酸化してIk60msの積層欠陥を有するシリ
コンウェーへ−管形成した。この場合1組02属が55
00ムの厚専に成長した。
First, dry the silicon crystals! 1 at 1100C inside
The silicon wafer was oxidized for 6 w# to form a silicon wafer having stacking faults of Ik 60 ms. In this case, one set of genus 02 is 55
He grew up to be a 00m thick college student.

第11iiIに示すように、この試料を、団墨の分圧を
5kl/cs”から10−#I4/Jま7変化専せて1
150Cで411=間熱J611t、た。比軟のために
、洲墨分圧が零の条件下で試料を熱J611した。菖1
a中において―線Aで示すウェーハー表面に8102膜
(勧5soojL)がある試料を用いて熱処理をした場
合には%NH,分圧が為くなるに従って、積層欠陥が成
長していることが秘められる。なお、自lsBで示すよ
うに表面に5tO2膜のないウニルバーでは、 NH3
分圧(満腹)が^くなるにつれて積層欠陥の収縮が急速
に起ることが認められる。1150t:’で5時間NH
As shown in Section 11iii, this sample was treated by changing the partial pressure of the group ink from 5kl/cs'' to 10-#I4/J by 7.
411=temperature J611t at 150C. For specific softness, the sample was heated under conditions of zero partial pressure. Iris 1
In case of heat treatment using a sample with 8102 film (5soojL) on the wafer surface shown by - line A in a, it is hidden that stacking faults grow as the partial pressure of %NH decreases. It will be done. In addition, as shown by self-lsB, in Uniru bar without 5tO2 film on the surface, NH3
It is observed that as the partial pressure (fullness) increases, the stacking faults shrink rapidly. 1150t: 'NH for 5 hours
.

熱処理では、七曾セ菅積層欠陥の完全消滅がしばしば認
められた。他方、この条件でのN2熱処理では10時間
以上を賛していたので、処j!時間の大巾な短縮が可能
である。
During heat treatment, complete disappearance of the Nanaso-Sekan stacking faults was often observed. On the other hand, N2 heat treatment under these conditions was recommended for more than 10 hours, so Significant time savings are possible.

次に、使用する試料番こおける8飯02膜の厚みを変え
て、1150C,1100tl’および1050Uで4
時間それぞれ熱処理をして積層欠陥の長さを#j定した
。その結果を第2図に示す。第2図において、―線Cは
1150tl’での熱処理、曲線りは1100Cでの熱
処理および曲線Eは1050Cでの熱処理の場合をそれ
ぞれ示す。これらの結果から、ウェーハー表面の810
.膜の初期厚が約1501以下  、でないと積層欠陥
を抑制する効果はなく、引02膜がない場合には積層欠
陥は生じないことが認められた。
Next, we changed the thickness of the 8-layer 02 film in the sample number used, and 4
The length of the stacking fault was determined by heat treatment for each time #j. The results are shown in FIG. In FIG. 2, the - line C indicates heat treatment at 1150 tl', the curved line indicates heat treatment at 1100C, and the curve E indicates heat treatment at 1050C. From these results, it can be seen that 810
.. It was found that unless the initial thickness of the film was about 1,501 mm or less, there was no effect of suppressing stacking faults, and that stacking faults did not occur in the absence of the 02 film.

また、第2図において使用した試料を用いて、初期5i
o2膜厚および熱処理温度゛を変えた場合の積層欠陥の
密度(デンシティ)を測定し、その結果を第6図に示す
。これらの結果からも、初期810゜膜厚が約150A
以下でないと積層欠陥が減少しないことが’FilI1
4t、た。
In addition, using the sample used in Fig. 2, the initial 5i
The density of stacking faults was measured when the O2 film thickness and heat treatment temperature were changed, and the results are shown in FIG. From these results, the initial 810° film thickness is approximately 150A.
If the stacking faults are not less than 'FilI1
4t.

更に、厚み5500ムのfs102膜を有するシリコン
結晶試料と′8!02膜を有しないシリコン結晶の試料
を用いて、NHlまたはヒドラジン類での処理時間、す
なわち窒化処理時間と積層欠・陥の長さとの関係を調べ
た。その結果を第4rIAに示す。なお、図中において
、−線F〜■は熱処理温度がそれぞれ、1050U、1
100G、1150t:’および1200t:’を示し
、また−線J〜Lは熱処理温度がそれぞれ1050C,
1100C詔よび1150Cを示す。第4図の結果によ
れば、810.膜を有しないシリコン結晶では、熱処理
することにより、しかも高温。
Furthermore, using a silicon crystal sample with a 5,500 μm thick fs102 film and a silicon crystal sample without an '8!02 film, we investigated the treatment time with NHL or hydrazines, that is, the nitriding treatment time, and the length of stacking defects/defects. I investigated the relationship between The results are shown in 4th rIA. In addition, in the figure, - lines F to ■ indicate heat treatment temperatures of 1050 U and 1, respectively.
100G, 1150t:' and 1200t:', and - lines J to L indicate heat treatment temperatures of 1050C and 1200C, respectively.
1100C edict and 1150C are shown. According to the results in FIG. 4, 810. Silicon crystals that do not have a film can be heat treated at high temperatures.

例えば1150Gないし1200Gで処理することによ
り、短い窒化処理時間で積層欠陥の長さを短縮できるの
に対して、5500A厚の810.膜を有するシリコン
結晶では、熱処理することにより、しかも1050Uで
熱処理することによつ、でも積層欠陥の長さが逆に長く
なり、1150Cという高温では窒化4611時間が短
くても積層欠陥の成長が急速に起ることが判明した。す
なわち、NHsなどの高温雰囲気中で熱処理することに
よって、数十Aのシリコンオキシナイトライドがシリコ
ン結晶表面に形成され、この膜が保護膜−となって、そ
のシリコン結晶からなる半導体基板の表面を平滑かつ清
浄に保持している。
For example, by processing at 1150G to 1200G, the length of stacking faults can be shortened with a short nitriding time, whereas 810. In a silicon crystal with a film, heat treatment at 1050U increases the length of stacking faults, and at a high temperature of 1150C, even if the nitriding time is short, stacking faults do not grow. It turns out that it happens quickly. That is, by heat treatment in a high-temperature atmosphere such as NHs, silicon oxynitride of several tens of amperes is formed on the surface of a silicon crystal, and this film becomes a protective film that protects the surface of a semiconductor substrate made of silicon crystal. Keeps it smooth and clean.

前述したように、この発明に係る中導体基板処理法によ
れば、従来の高温処m+こよる結晶欠陥および結晶欠陥
の発生核除去における宍面粗、汚染の問題が解決される
と共に、より低温でかつより早く所望の効果が得られる
As mentioned above, according to the medium conductor substrate processing method according to the present invention, the problems of surface roughness and contamination in the removal of crystal defects and generation nuclei of crystal defects caused by conventional high-temperature treatment can be solved, and The desired effect can be achieved more quickly.

【図面の簡単な説明】[Brief explanation of drawings]

第1〜4図はこの発明に係る方法の条件をそれぞれ示す
グラフである。 代理人 上屋 勝 第3図 ネ71  其R5t(h  Ill  (A〕第4図
1 to 4 are graphs showing the conditions of the method according to the present invention, respectively. Agent Masaru Ueya Figure 3 Ne71 Its R5t (h Ill (A) Figure 4

Claims (1)

【特許請求の範囲】[Claims] 半導体基板をNHs1ヒドラジン蒙または庫暴もしくは
ヒドラジン1llf−會む不m*ガスの寥■気やまたは
プラズマ雰囲気中で熟鶏履するこ七を轡黴とする牛導体
基板魁履法。
A method for manufacturing conductor substrates in which a semiconductor substrate is exposed to NHs1 hydrazine or hydrazine 1llf in a gas atmosphere or in a plasma atmosphere.
JP4801482A 1982-03-25 1982-03-25 Treatment of semiconductor substrate Granted JPS58164229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4801482A JPS58164229A (en) 1982-03-25 1982-03-25 Treatment of semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4801482A JPS58164229A (en) 1982-03-25 1982-03-25 Treatment of semiconductor substrate

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP6193607A Division JP2601208B2 (en) 1994-07-26 1994-07-26 Semiconductor substrate processing method

Publications (2)

Publication Number Publication Date
JPS58164229A true JPS58164229A (en) 1983-09-29
JPH0568099B2 JPH0568099B2 (en) 1993-09-28

Family

ID=12791447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4801482A Granted JPS58164229A (en) 1982-03-25 1982-03-25 Treatment of semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS58164229A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123098A (en) * 1985-11-22 1987-06-04 Toshiba Ceramics Co Ltd Silicon single crystal
JP2002334848A (en) * 2001-05-09 2002-11-22 Sumitomo Mitsubishi Silicon Corp Thermal treatment equipment for silicon wafer
JP2003031582A (en) * 2000-11-28 2003-01-31 Sumitomo Mitsubishi Silicon Corp Manufacturing method for silicon wafer and silicon wafer
JP2003124220A (en) * 2001-10-10 2003-04-25 Sumitomo Mitsubishi Silicon Corp Method for manufacturing silicon wafer and silicon wafer
JP2009170940A (en) * 2009-04-30 2009-07-30 Sumco Corp Semiconductor wafer manufacturing method, and semiconductor wafer
JP2009212537A (en) * 2000-11-28 2009-09-17 Sumco Corp Method for producing silicon wafer and silicon wafer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5712524A (en) * 1980-06-26 1982-01-22 Fujitsu Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5712524A (en) * 1980-06-26 1982-01-22 Fujitsu Ltd Manufacture of semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123098A (en) * 1985-11-22 1987-06-04 Toshiba Ceramics Co Ltd Silicon single crystal
JPH0561240B2 (en) * 1985-11-22 1993-09-03 Toshiba Ceramics Co
JP2003031582A (en) * 2000-11-28 2003-01-31 Sumitomo Mitsubishi Silicon Corp Manufacturing method for silicon wafer and silicon wafer
JP2009212537A (en) * 2000-11-28 2009-09-17 Sumco Corp Method for producing silicon wafer and silicon wafer
US7670965B2 (en) 2000-11-28 2010-03-02 Sumitomo Mitsubishi Silicon Corporation Production method for silicon wafers and silicon wafer
JP4720058B2 (en) * 2000-11-28 2011-07-13 株式会社Sumco Silicon wafer manufacturing method
JP2002334848A (en) * 2001-05-09 2002-11-22 Sumitomo Mitsubishi Silicon Corp Thermal treatment equipment for silicon wafer
JP2003124220A (en) * 2001-10-10 2003-04-25 Sumitomo Mitsubishi Silicon Corp Method for manufacturing silicon wafer and silicon wafer
JP2009170940A (en) * 2009-04-30 2009-07-30 Sumco Corp Semiconductor wafer manufacturing method, and semiconductor wafer

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Publication number Publication date
JPH0568099B2 (en) 1993-09-28

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