JPS58159127A - Memory controller - Google Patents

Abstract

PURPOSE:To ensure the effective use of a memory bank at a memory access path of multistage switch constitution, by reserving the timing of access request and eliminating the queuing in the course of an access bus. CONSTITUTION:The memory access request is set to a register Rxx in a memory controller MMC from each device. The access requests to memory devices MM0 and MM1 are set to memory registers MR0 and MR1, respectively. The access requests given from channel devices CH0-CH15 are set to register ARxx by switches SW0-SW3, and two registers ARx0 and ARx1 are provided to each switch. Then an unreserved access request and a reserved access request are set to the registers ARx0 and ARx1, respectively. The register ARx1 is connected to the registers MR0 and MR1 via a priority circuit PR.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a memory control device, l#, and a memory system used in a computer. Regarding equipment.

[Prior art]

Conventional memory control device 11 central processing unit, channel! Controls access to memory from devices when memory is shared by multiple devices such as tilt and input/output devices.

Figure r41 is a block diagram containing a conventional row, where channel equipment ItL:1-iQ ~C)i3 is a block diagram containing a row of channels.
W Q * 8 W 1 is connected to the memory controller (i1
MMcr/c is connected.

L/') sp A RQ * A ki= l is a register in which an access request is set, and
U has memory banks BKO and BK-1.

Channels fcIfCHo and C) on switch 45w0
When there are 4 access requests for il, the channel device IfCH
The setting is such that o wins (the channel equipment [Uh□'s 1 priority is high).

Similarly, switch 8VV1 has channel device 1101 (
The priority of 0 and 0 is set to high.

With the above settings, a time chart is shown in FIG. 2 when channels @@CH□ to CH3 issue an access request 9Ct-ig-LE CH3 in the same cycle. Register A shown in Figure 2
The values shown on the time chart for R□, ARI, and memory bank BkQ*HKl are as follows.

It shows which channel device L;MO-U)i3 is using these channels for access/request.

Figure @2 shows that the access request of channel device tCH3 is not processed at all even though there is free time in the bank.
It shows that it is not. This is a channel robe #It
Before eH3's access request kccH3 is set in register AkLl, access request RCH2 from primary channel device #tel-12 is issued and channel device CFi2 is sent.
Since the priority of 1 is high, this value is set in register AkLl and register A is set in register A.

The memory access path configuration shown in FIG. 1 has the drawback that bank free time cannot be used effectively as described above.

8g3 As shown in the diagram, each channel equipment +t CM O~U
i-13I has 14 separate memory access paths, channel device L:)io-C) access request Re from i3
)Ig~R1:)i3 and each memory bank 1jKQ,
When controlling the busy 1f- of BKI all at once, the second
Although the drawbacks shown in the figure are eliminated, the number of access paths, switch circuits, and control circuits increases.

By making a continuation device, such as a channel device, reserve in advance and eliminating the cost of waiting in the middle of the access path, the above-mentioned drawbacks of the memory access path with a multi-stage switch configuration can be eliminated, and the memory nozzle ( It is an object of the present invention to provide a memory control device t that can effectively utilize and control links.

[Structure of the invention]

The memory control device t of the present invention includes an access reservation table that displays access reservations for each clock of the memory bank;
an access reservation generation means for receiving an access reservation request, extracting an unreserved clock close to the requested time from the access reservation table and generating an access reservation for -S acceptance in the access reservation table; and the access reservation generation means. The apparatus includes a reserved time returning means for returning the reserved time of the access reservation generated by the means, and an unreserved access prohibition means for prohibiting unreserved access from using the reserved time slot.

In other words, the memory control device of the present invention has an access reservation table that displays access reservations for each clock of a memory bank, and upon receiving an access reservation request, extracts an unreserved clock close to the requested time from the access reservation table and makes an access reservation. , means for returning the time when the reservation has been made, and means for carefully preventing unreserved access from using the reserved time slot.

[Explanation of examples of real power]

Next, a practical example of the present invention will be explained in detail with reference to FIG. [fi].

FIG. 4 is a block diagram containing one embodiment of the present invention.

The configuration of memory access paths in the system is shown.

In the culvert 4 diagram, el'Lt's central processing system, t, t, n
.

1 to U) 115 is a channel device. M IVI C
A memory control device #, MIVQ and MM1 are memory devices each consisting of four banks HKQ to BK3.

Register Ahxx in memory control device tMMC is a register in which memory access requests from each device are set, and memory registers MftQ and MRI/#'i
The access request sent by the memory device dMM□ and MMIK is set.

Priority circuit 1'R is register A k4Jxx
Among the NFT access requests set in , the one whose memory banks BK□ to HK3 are not busy and which has a high priority is selected.

Priority is register number x of register number
The smaller x is set higher, and the central processing unit 1i
Register AR4 that stores access requests from CPLJ
0gakyo is also close to priority.

Channel 4#'C)10. C) Is the access request from i15 to switches SvV□ to δW3? L-through register A
It is set to hxx, but one switch is set to t.

Two registers A, RXOI, A, and RIXI are provided. Register ARXO is a register that sets unreserved access requests, and register AmzO is a register that sets unreserved access requests.
x is a register that sets reserved access requests.

Note that the register ARXI is a priority circuit P)Lt
l-memory register M)LQ without intervening.

This is because the reserved access request is guaranteed to have no conflict with the reserved access request of the pool at the time of reservation.

The switch svvO-swl is set to give priority to the reserved access request when there is a conflict between a reserved access request and an unreserved access request. The unreserved access request is set in the register ARIXO only when the register ARXO is empty and the reserved access request does not use the switch.

By the way, there is no register A RIXI in the access path of the central processing unit 1tet'u or b.This is the central processing unit, and the access from the PU is based on the timing of issuing the next access request and the bank to be accessed. This is because there are few cases where this is possible.

On the other hand, in the case of data transfer from the channel devices ChO to U) 115, the transfer rate is constant depending on the connected device, and the data is sequentially transferred to consecutive memory areas.

Therefore, the timing of access requests and the banks used from the start to the end of data transfer can be accurately predicted. A register ARXO is provided to handle unpredictable access requests from the channel device Uni□-UH15.

Processing of access reservation requests from the channel devices tCHO to ett15 is performed using the memory access path shown in FIG. 4 instead of having a special interface for this purpose. First, to start a reservation in an unreserved state, a reservation start command is set in the register ARxo.

It will be processed. - Confidential reservations and subsequent reservations 4
The designation of cancellation or reservation is included in the access request, and the previous access request makes the next access reservation.

The control of the memory m control device MMC is performed in units of clock a), small cycle S, and large cycle L2.

FIG. 5 shows the cycle relationship and names of the small cycle S and the large cycle L. The small cycle S is the cycle SQ~Si
T deme 9. These 10 cycles constitute one large cycle L. Moreover, the large cycle L is four cycles of cycles LQ to L3.

Note that the time memory for one small cycle S is in bank BKO.
- Matches the memory cycle time required to process one access request in Bk3.

@6 As shown in FIG. 6, the small cycles S of each memory bank BKO to BK3 are set by n clocks each.

In the above embodiment, the channel devices]teHo~Ut(15
The data transfer between the memory device MMQ/MMI is 8 bytes.
There are three types as shown in Table 1.

Table 1 This device type and the allocation of small cycles S and large cycles L are controlled as follows.

One small cycle 8 is allocated for every 2% large cycle L of the device of type ■.

Type ■ device: Allocate one small cycle 8 of normal cycles LO and L2. However, if these cannot be allocated, one small cycle S of cycles L1 and L3 is allocated.

Type C device: Allocate one small cycle 8 of normal cycle LO. However, if cycle LO cannot be allocated, one small cycle 8 of cycle 14 is allocated.

Small cycle S [Once assigned, the same number is assigned until the transfer is completed. In the above allocation, when the data transfer is in the address increasing direction, the small cycles 82 to S7 are allocated, and when the address is decreasing, the small cycles S8 and δ9 are allocated to fullJD, and the small cycles SQ and δ1 are not allocated. The reason why the small cycles SO and 81 are left open is because processing time is required for processing unreserved accesses and switching to the large cycle L.

FIG. 87 is a block diagram showing details of the priority circuit in the embodiment shown in FIG. 4.

In addition,#! Figure 7 shows the memory control circuit HMC shown in Figure 4.
Only a part of the circuit in the figure that is related to the present invention is shown.

In the figure, an input signal 100 is a signal generated from a reservation start command, and includes the channel number, path number, memory device number, and access direction for which reservation is requested. The bus number is the switch S VV g -S shown in the diagram @4.
This number corresponds to the number of W3. Further, the access direction indicates whether data transfer is performed in the direction in which the memory address increases or in the direction in which the memory address decreases. signal 10
1 is a signal created when the reserved adjacent access *X specifies a reservation for the next access, and is the same as the input signal 100 except that it does not include the access direction. The signal 300 includes the numbers of the large cycle L and the small cycle S that were reserved as a return signal to the reservation start command. signal 200~2
07 Kesonnzonn Memory device folding MM□'s memory bank BK
O to BK3 and memory device J[Ml's memory bank B
KQ to BK3KN, and is a signal to stop unreserved accesses from using the memory banks during the time period when the corresponding memory banks are reserved.

Register files 10-14 each have their own functions.

Register file IO: consists of 8 registers in the access reservation table.

One bit indicates whether or not one small cycle S of one bank is reserved. One register is 40 bits.
The reservation of one large cycle L (10 small cycles S) of one memory 4t-+1 (4 banks) is displayed.

Register file 11: A bus reservation table consisting of 16 registers. 1 bit for 1 bus
The presence or absence of a clock reservation is displayed. One register has 40 bits and indicates the reservation of one major cycle L (40 clocks) of one bus.

Register file 12: Channel status table 164
It consists of 161 registers. One register corresponds to one channel device and displays the type of device connected to the channel device, the access direction, and the cycle number reserved by the reservation start command.

Register file 13: An access management table consisting of four registers of 40 bits.The portion of the access reservation table corresponding to cycles LO and Ll is copied by each company at the start of cycles LO and Ll.

Register file 14: Nox management table, consisting of eight 40-bit registers.

The portions of the path reservation table corresponding to cycles L, Q and Ll are then copied at the beginning of cycles LO and Ll.

After an access reservation is made in response to a reservation start command, the following rounding process is performed to guarantee the access cycle for continuous shooting of that channel device. The assignment of large cycles L differs depending on the type of device, and cycles LQ and Ll are often used and used, so
If there are 9 cycles in cycle LO or Ll, the corresponding cycle Fi of cycle L2 or &:tL3 is an empty cycle. Therefore, when starting a reservation, it is necessary to know the reservation status of the previous cycle LO and Ll and the subsequent added:rtfc reservation cycle, and for this purpose, the access management table and node ffi table are used for one history. be.

When the input signal 100 is set in the register 40 by the reservation start command, the state of the corresponding cycle LO is determined from the bus management table and the access management table using the set data (bus number and memory number). Output n.Multiplexer circuit 33.34Fi.

In the read cycle t according to the bank number and memory access direction of the register 40, the memory bank and clock wipe for which reservation is requested is selected among the 0 states and sent to the OR circuit 72.

, M circuit 72 outputs are all "L", indicating that there is no empty cycle. If there is one or more empty cycles in the output of the OR circuit 72, the encoder 71 outputs the entire code of the cycle number of one of the small cycles S,
Set in register 70. Multiplexer circuit 23
+24 is selected by the cycle number to the bank number, so that the bit corresponding to the number of the selection signal becomes "1", and the other signals output the outputs of the multiplexer circuits 33 and 34 as they are. By setting this output to the register files 13+14, the same cycle is prevented from being reserved twice until the next cycle LO.

If there is no vacancy in the cycle LO, and the type of the connected device is other than I, the state of the cycle Ll is O'km and the same process as above is performed. If the quaternary device type is ■ and there is no empty cycle in cycle LO, and if the connected device type is I or I
If there is no empty cycle in either cycle L Ot L 1, the reservation cannot be started.A code indicating that the reservation cannot be started is set in the register 42.

As described above, the reservation of the small cycle S of the small cycle 8 is determined from which cycle L Ot L 1 was reserved and the large cycle L being executed at that time. Counter 52f'j: Displays the large cycle Ltl that is constantly being executed. The encoder 75 is the counter 52
output, the device type read from the channel status table, and the large cycle L when the small cycle S is reserved.
Enter the cycle number of the large cycle L to be reserved.

Through the above operations, the cycle numbers of the small cycle S and large cycle L to be reserved are set in the register 70. Next, these reservation indications are set in the access reservation table, bus reservation table, and channel state status. Multiplexer circuit 20
22, the reservation display corresponding to the register 70 is added. This completes the processing for the reservation start command.

A reservation sequence for reserving the next access at the time of an access request after the start of reservation is performed by setting the signal 101 in the register 41. In this case, since the same number is conveniently used for the small cycle S, there is no need to set it to #, and it is read from the channel status table. The large cycle L is generated by the encoder 75 in the same way as the reservation start command processing. The bank number set in the register 41 is the bank number to which an access request is issued at that time, and is not the bank number for the next access reservation. The numbing circuit 73.74t-t determines the reservation bank number ti for the next access from the access request bank number and the access direction. The reservation is continued by displaying the reservation corresponding to the cycle number of the large cycle L and the cycle number and bank number of the small cycle S in the access reservation table and the bus reservation table.

At the timing of switching of the large cycle L that is being executed.

The parts of the access reservation table and bus reservation table corresponding to the new large cycle L are read out.

The n registers 80 and 81 are set, respectively, and the read portion of the retable is cleared. The counters 50*51 are counters that display 8 cycles of each memory bank, and the reservation number 16 of each memory bank, which is ε6 for the small cycle S displayed by the counter 50+51, is output to signals 200 to 207.n, each memory bank Is the reserved time slot used for unreserved access? I leave you with nuru. The small cycle 8 displayed by the counters 50 and 51 is running at a phase three clocks earlier than the small cycle S being executed in each memory bank.

Therefore, signals 200 to 207 output an unreserved access prohibition signal at a phase three clocks earlier than the reserved time slot of each bank.

In γL, the timing at which a request for unreserved access is issued is asynchronous with the small cycle S of the memory bank.

This is because, in order for the unreserved access memory cycle (4 clocks) and the reserved access not to collide, the unreserved access must be issued at least 4 clocks earlier than the reserved access time slot.

A signal 208 is a signal indicating the path reservation state set in the register 81, and this signal is set in the register ARx shown in FIG.
It is used to control the switch circuit on the path between x and memory register MRX.

〔Effect of the invention〕

The memory control device of the present invention controls memory access.

[Brief explanation of drawings]

Fig. 1 is a block diagram including an example of a conventional memory control device, Fig. 2 is a time chart of memory access in the conventional example shown in Fig. @1, and Fig. 83 is a block diagram including a row of ponds of a conventional memory control bond. Fig. 4 is a block diagram including an embodiment of the present invention, Fig. 5 is a time chart showing the cycle relationship in the leprosy case shown in Fig. 4, and Fig. 6 is a small cycle shown in Fig. 5. A friend's time chart explaining the details. FIG. 7 is a partial detailed block diagram of the priority circuit shown in FIG. 4. Cl-1Q~C) i15... Channel device, s
w□~SW3...Switch, MMC...
・Memory control device, MMU1MMo9MMl... Group ・Memory device, AkL. ~A) 1,3, ARO□ 5-AR40...
register. )'R...Priority circuit l path, fjkQ
~MK3...Memory puncture, MI:L□, MR
I...Memory register, epu...Central processing unit. L...Large cycle, 8...Small cycle, LQ~L3,5O-89...cycle,'l
'······clock. )1. )IQ~BonCH3...Access request,
lO~14...Register file, 20~24
33 * 34... Multiplexer circuit, 40
〜42・・・・・・Register, 50～52・・・・・・
Counter, 60-67...Multiplexer circuit, 71.75...°...Encoder, 72...
・Ethical sum circuit, 73*74... Pain-causing circuit, 70
,80s81...Register. Figure l, 4th room, 5th figure, cod figure 6

Claims (1)

[Claims] An access reservation table that displays access reservations for each clock of a memory bank, and an access reservation for searching unreserved locks 'IIt+li near Yasugi time from the access reservation table in response to an access reservation request and displaying them on the access reservation table. an access reservation generation means for generating an access reservation; a reservation time return means for returning the reservation time of the access reservation generated by the access reservation generation means; Memory characterized by including unreserved access Qin Zheng means? ff1J#4! &.