JPS58143605A - Frequency dividing and multiplying circuit - Google Patents

Abstract

PURPOSE:To divide or multiply the frequency, by writing a digitized input signal to a random access memory with a writing control pulse and then reading the input signal with a reading control pulse having a different period from the writing control pulse. CONSTITUTION:The analog signal of an input terminal (a) is supplied to an A/D converter 1. A switch circuit 3 selects the writing and reading timings to a random access memory 2. A switch circuit 4 selects the input timing of both writing and reading control pulses CNT1 and CNT2. The output of the converter 1 is written to the memory 2 by the pulse CNT1, and then the contents of memory 2 is read by the pulse CNT2 and fed to a D/A converter 6 via a latch circuit 5. The pulse CNT1 advances synchronously with a signal R/W having a period T; while the pulse CNT2 advances synchronously with a clock pulse CP having a period tau. A signal is obtained at an output terminal (e) with multiplication by a multiple that is decided by T/tau or with division.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency multiplier circuit that multiplies or divides a frequency.

Phase lock circuits, loop circuits, LC resonant circuits, and the like are known as conventional frequency multiplier circuits. However, the phase-locked loop circuit is only capable of frequency multiplication of one wave of variable frequency input, and the LC resonant circuit has a fixed input frequency and output frequency. For this reason, conventional frequency multiplier circuits cannot multiply or divide complex waveforms by superimposing multiple frequencies.

An object of the present invention is to provide a frequency multiplier circuit capable of multiplying or dividing a waveform of an arbitrary frequency.

To achieve the above object, the present invention writes a digitized input signal into a random access memory using a write control pulse in a frequency multiplier circuit that multiplies or divides one frequency, and then writes this random access signal into a memory using a write control pulse. , the signal stored in the memory is read out using a readout control pulse, and at this time, a signal obtained by multiplying or dividing the input signal frequency by a ratio of the cycle of the write control pulse and the cycle of the readout control pulse is output. It is characterized by

The present invention will be specifically described below with reference to the accompanying drawings which are examples. FIG. 1 is a block diagram of a frequency doubling circuit according to the present invention. In FIG. 0, 1 is an analog-to-digital converter. This analog-digital converter 1 converts an analog signal input to an input terminal a into a (1 to n) bit digital signal and outputs the digital signal.

2 is random, access, memory. This random access memory 2 has a multi-bit configuration word of (N words)×(n bits).

3 is a random access from the analog-to-digital converter 1, writing a digital signal to the memory 2, and a random access.
This is a switch circuit that selects the timing between access and reading from the memory 2, and is configured with n switches SW1 to SWn corresponding to n-bit digital signals.

Reference numeral 4 designates a switch circuit for selecting the input timing of random, access, and write control pulse CNTl and read control pulse CNT2 for the memory 2, and the m-bit (2f
l=N) write control pulse CNT1. It has an S configuration corresponding to the read control pulse CNT2. The control pulses CTI and Cr2 control the random, access, write and read addresses of the memory 2, respectively.

5 is a latch circuit. This latch circuit 5 latches the read data one clock ago, and outputs the read data at the next timing. Also, at the write timing, the read data one clock previous is held and output.

6 is a digital-to-analog converter. This digital-
The analog converter 6 may be provided as necessary to obtain an analog signal output, and b is the write control pulse CNT.
l is the input terminal, C is the input terminal for the read control pulse CNT2, d is the terminal for inputting the read/write control signal (hereinafter referred to as R/W signal), e is the analog signal output terminal, f is the digital signal output terminal It is.

Next, the operation will be explained with reference to the time chart shown in FIG. First, at the timing shown in FIG. 2(d), R/W
A signal is input to terminal d. At the timing when R/W@ becomes logic 1, S W 1- S W of switch circuit 3
n contacts are analog-to-digital converter 1 and random;
Contact is made between 5t-52 that connects the access and memory 2, and SWn+1 to SWn+ of the switch circuit 4
The contact point of m contacts the input terminal of the write control pulse CNTl between 34 and 35, which connects the input terminal of the write control pulse CNTl to the random access memory 2 (Fig. 2(e)). Therefore, the R/W
At the timing of the logic l of the signal, the digital signal output from the analog-to-digital converter 1 is randomly accessed and written to the memory 2 (FIG. 2(f)), and the R/W signal becomes logic 1 with a period T. The time length at which the logic 1 is reached is equal to the period τ of the clock pulse Cp in FIG. 2(a). On the other hand, the write control pulse CNTl controls the random access and write address of the memory 2, and advances in synchronization with the R/W signal. therefore,
The output of analog-to-digital converter l is:

At Jm period T, data is randomly accessed and sequentially written from address 0 to address (N-1) in memory 2 (Fig. 2(f)).
As a result, the digitized input waveform is randomly accessed and stored in the memory 2.

On the other hand, at the timing of logic 0 of the R/W signal, the contacts SWI to S W n of the switch circuit 3 contact between 31 and 33 that connect the random access memory 2 and the latch circuit 5, and the switch circuit 4 SWn'+(~S
W n + m contact connects input terminal C of read control pulse CNT2 to random, access, memory 2 S
4-36 (Fig. 2(e)). Therefore, random access is performed at the timing of logic O of the R/W signal.

Reading from memory 2 is performed (Fig. 32(f)),
Random, access, reading from the memory 2 is performed by addressing with a read control pulse CNT2, which is a clock pulse CNT2.
It is moving in sync with P. Furthermore, when the R/W signal is at logic 1, the latch circuit 5 holds and outputs the data read l clock ago. Therefore, the read cycle from access 9 memory 2 is
It is equal to the period τ of the pulse CP.

As a result of the above operation, the input signal is written into the random access memory 52 at a period T and read out at one period. Therefore, the digital output signal is obtained by frequency-multiplying the input signal by T/τC=Q). This digital output signal is led to the output terminal e via the latch circuit 5 and the digital-to-analog converter 6, or directly to the output terminal f from the latch circuit 5, and is multiplied by the frequency of the analog signal input to the input terminal a. The frequency is extracted as an analog signal or a digital signal. In this embodiment, the case where the input frequency is multiplied by a factor has been explained as an example, but the write control pulse CNTl and the read control pulse CNT
It is also possible to divide the frequency by reversing the relationship between the two periods.

Since the frequency doubling circuit according to the present invention has the above-described configuration, no matter what the frequency and waveform of the input signal, it can be divided into the period T of the write control pulse CNTl and the period T of the read control pulse CNT2. It is possible to faithfully multiply or divide the frequency by a multiple determined by the ratio (T/τ). Moreover, the linearity of the output waveform depends on the number of bits of the analog-to-digital converter l, random access, memory 2
There is also the advantage that it can be easily set to a required value by selecting the number of word configuration bits.

As described above, the present invention writes a digitized input signal into a random access memory using a write control pulse in a frequency multiplier circuit that multiplies or divides a frequency, and then writes this random access signal into a memory using a write control pulse. The signal stored in the memory is read out using a readout control pulse, and at this time, a signal obtained by multiplying or dividing the frequency of the input 5 signal by a ratio of the cycle of the write control pulse and the cycle of the readout control pulse is output. Therefore, it is possible to provide a frequency multiplier circuit capable of multiplying or doubling any frequency or waveform.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a frequency doubling circuit according to the present invention, and FIG. 2 is a timing chart of each part. 1...-Analog-digital converter 211...Random, access, memory 3.4 Fist/switch circuit 5/Φ/latch circuit 6...Digital-analog converter 2E

Claims (1)

[Claims] (1) In a frequency doubling circuit that multiplies or divides a frequency, a digitized input signal is written into a random access memory by a write control pulse, and then the said signal is stored in the random access memory. is read out by a read control pulse, and at that time, a signal obtained by multiplying or dividing the input signal frequency by a ratio of the cycle of the write control pulse and the cycle of the read control pulse is output. Double circuit.