JPS58149550A - Accessing system of memory - Google Patents

Abstract

PURPOSE:To switch a bus line instantaneously with the same priority level, by transferring the bus line to a microcomputer, which accesses a memory earlier than the other, out of plural microprocessors and holding microprocessors, which access the memory later, to store their requests. CONSTITUTION:When a microcomputer muCM A out of plural muCMs turns on an access request signal CS1 to a memory MEM, the request from the muCM A is transmitted to FFs 1 and 2 through an AND gate AD only when a signal CS2 of a muCM B is not turned on, and a bus controller BC 1 connects an address bus ADR1, a data bus DAT1, and a write signal WR1 to the memory MEM, and the FF 2 turns on an accessable response signal RD1. In this state, when the muCM B turns on the request signal CS2 to the memory MEM, an FF 3 is not set, and a response signal RD2 is not turned on, but the bus line of the muCM B is held in the state of access to the memory MEM. When the signal CSI is turned off after the access of the muCM A is terminated, FFs 3 and 4 and the signal RD2 are turned on, and the bus line of the muCM B is connected to the memory MEM instantaneously.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory access method in a system in which a plurality of microcopy computers access the same memory.

In general, in a system in which a plurality of microcomputers access the same memory, it is necessary to provide mutual interlock to prevent conflict between the two pass lines. Now, A.

B Mutual A between two microcomputers. Lid 1
The form of 0tsuku is the above-mentioned microcomputer A,
If BK priority is set and both access the same memory at the same time.

The pass line of microcomputer A with high priority is connected to the memory, and the pass line of microcomputer B with low priority is issued by issuing a 70-ting request (hold signal for Intel microcomputers) for the pass line. After A completes the access, release the floating request and move the memory path line from A to B.
It is configured to switch to

By the way, in the conventional method described above, it is necessary to prioritize each microcomputer.

Each microcomputer cannot access memory with the same priority. In general, a microcomputer only recognizes the request or release of a floating request signal for a pass line at a specific timing during a processing cycle, so it has the disadvantage that switching of pass lines cannot be done instantaneously, and the processing time increases accordingly. are doing.

The present invention has been made to solve these conventional drawbacks, and the memory access priority is determined simply by whether the access request from the microcomputer is early or late. The inaccessible microcomputer sets the pass line to 70-
The purpose of this invention is to provide a memory access method that allows a pass line to be connected to memory immediately after the accessing microcomputer completes processing by holding the pass line in the memory access state without putting it in the memory access state. .

An embodiment of the present invention will be described below with reference to the drawings. Note that FIG. 1 shows the circuit, and FIG. 2 shows the timing chart.

In the figure, C81, an access request signal to the 2Fi memory MEM, RDl, a response signal indicating that the 2ij memory can be accessed, ADHl, 2. DATI, 2°WRI, 2
Each microcomputer or computer address bus, data bus, memory write signal, FF1 to FF+tff
Fritsnofloraph, respectively.

R8T, C! LK is a reset signal and a clock signal that control these flip-flops.

AND gate, OR gate, and inverter gate each consisting of an IC for AD, OR, and IV.

BC is a bus controller that connects only one of the pass lines from multiple microcomputers to the memory MEM. In addition, the above O8゜RD, ADH, DAT, WR
As for the numbers attached to the subscripts, 1 indicates what is controlled by microcomputer A, and 2 indicates what is controlled by microcomputer B.

Now, one of the microcomputers is A.

When the access request signal C8l is turned on when attempting to access the memory MEM, the request from the microcomputer A is sent to the flip-flop only if the access request signal 082-i is not turned on in the computer A and the microcomputer B. FFI, inform IT'F2,
Connect the pass line of the memory MEM to A and turn on the accessible response No. 8 RD1. If microcomputer B has already turned on C82 and is accessing the memory MEM when microcomputer A turns on C81f, the flip-flop FF is switched on by AD.
i, FF2ij is not turned on.

The pass lines of the memory MBM are connected as a unit to the microcomputer B, and an accessible response signal RD is sent.
1ij-Do not turn on. At this time, the path line ij of microcomputer A is simply not connected to the memory IJ M EM, so it is not in a floating state, but is maintained in an accessing state (in the WA state in Intel microcomputers). C, Microcomputer A
is constantly monitoring RDi.

Therefore, when the access processing from microcomputer B is completed and the access request signal C82 is turned off, the flip-flops FF1 and FF2 are turned on, the path line of A is connected to the memory MEM, and the access-enabled response signal RDI is turned on. When turned on, A instantly writes a memo IJM.
It is possible to enter read and write access to EM.

This is because, in general, the time required to restart microcomputer processing from the floating state of the pass line and from the state maintained during access is overwhelmingly shorter in the latter.

The relationship with microcomputer A when microcomputer B accesses the memory MEMK is also the same, and the access priorities of both A and B are exactly the same.

Next, the above operation will be explained with reference to the timing chart shown in FIG.

In this figure, in order for microcomputer A to access memory MEM at time t1, access request signal C
When 8l is turned on, microcomputer B reads memory M.
Since EM is not being accessed, flip flop 1 is activated at time t2 in synchronization with the rising edge of clock OLK.
FF1-Q turns on, and as a result, microcomputer A
The path lines of are connected to the memory MBM.

Even if microcomputer B turns on access request signal C82 to access memory MEM at time t6, access signal 0EI from microcomputer A
2 is on, the C82H receiver cannot be attached, and the Fritub Fluorough-FF3-Q will not be on.

When the access request signal 081 from microcomputer A turns off at time t4, flip-flop -FF1-Q is activated at time t5 in synchronization with the rise of clock CLK.
is turned off, and at time t6, which is further delayed by half a cycle of clock CLK, flip-flop FF3-Q is turned on, and as a result, the pass line of microcomputer B is connected to memory IJ.
M Connected to BM.

As described above, the present invention provides a memory that is read and written accessed by a plurality of microcomputers, a bus controller that passes a pass line to the side that receives an earlier access request from the microcomputers, and a standby signal that issues a standby signal to the side that receives an earlier access request from the microcomputers.

Since a flip-flop is provided to store a request to pass the pass line to the slow side after completion of access on the early side, there is an effect that the pass lines from the plurality of microcomputers can be instantly switched according to the same priority order.

[Brief explanation of the drawing]

The figure is only for showing one embodiment of the present invention. FIG. 1 is a circuit diagram thereof, and FIG. 2 is a timing chart of each signal. In the figure, F'F1. II'F2. F'I+'3. F
F4 is flip frog, AI) i”r and gate,
OR is the OR gate, Engineering V is the inverter game), BC is the bus controller, MEMfi memory lJ, C8t. CEI2 is an access request signal, RDI and RD2 are accessible response signals, ADRl and ADR2 are address buses,
DATl and DAT2 are data buses. WRl and WR2 are a memory write signal, an R8Ti1r reset signal, and an 0LKij clock signal. Agent Shin Kuzuno −

Claims (1)

[Claims] Read from multiple microcomputers. Memory to be accessed by write, a bus controller that passes a pass line to the earlier side of access requests from the plurality of microcomputers mentioned above, and stores a request that sends a standby signal to the slower side and passes the pass line to the slower side after the access from the earlier side is completed. A memory access method characterized by instantaneous switching of path lines from multiple microcomputers with the same priority order.