JPS58120319A - Expanding circuit of pulse width - Google Patents

Abstract

PURPOSE:To set the accurate time of duration even with a pulse having long time of duration, by applying an input pulse to a bistable FF to actuate an oscillator with the output of the FF and dividing the oscillated output with a prescribed dividing ratio to feed it back to the FF. CONSTITUTION:When an input pulse A fed to a terminal 1, a bistable FF circuit 2 is set. Then a signal B is fed to an output Q. At the same moment, an oscillating circuit 6 is actuated to transmit a repeating pulse C of a fixed frequency. The pulse C is counted N times by a frequency dividing circuit 7, and a pulse D is fed to the output of the circuit 7 to reset the circuit 2. As a result, a short pulse A is expanded to an output terminal 2 and then transmitted in the form of an output pulse B. The circuits are formed digitally, and the time of duration of the output pulse is decided by the dividing ratio of the circuit 7 as well as the oscillation frequency of the circuit 6 and can be set accurately.

Description

[Detailed description of the invention] C@@t) Technical field to which it belongs] The present invention is a digital logic circuit, and relates to a circuit that sends out an output pulse that lasts for a predetermined time from the point in time when an input pulse is given. . In particular, the present invention relates to a pulse lengthening circuit that is suitable as a long-time circuit having a duration of, for example, one minute or more.

[Description of prior art]

FIG. 1 shows a block diagram of a conventional circuit.

An input pulse given to the input terminal IK is applied to the input 8 of a bistable flip-flop circuit 20, and its output q
It is led to the Fi output terminal 3 and is applied to the integrating circuit 40. The output of the integrating circuit 4 is given to a threshold circuit 5, and the output is fed back to the reset input RK of the flip-flop circuit 2.

In a circuit having such a configuration, when an input pulse that triggers the input terminal IK arrives, the flip-flop 1 and 2 rise, and at the same time, the integrating circuit 4 starts integrating the output voltage of the flip-flop circuit 2.

When the integral output reaches a predetermined threshold, the threshold circuit 5 sends out an output and the flip-flop circuit 2 is set. A high level signal from the output terminal 3KIfi is sent out only during the time when the flip-flop circuit 2 is rising.

Although this conventional circuit can extend the pulse width, the duration of the output pulse is determined by the time constant of the integrating circuit 40 and the threshold value set in the threshold circuit 5. Therefore, it is fine if the duration is short, but if a considerably long duration is required, the values of the resistor and capacitor of the integrating circuit 4 become large, and the circuit becomes large. Furthermore, the dark value of the analog voltage has poor accuracy and is susceptible to noise, and its duration cannot be accurately determined.

All of these have practical limits, and if the duration exceeds one minute, they cannot be realized as an integrated circuit with practical constants.

[Object of the present invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pulse width stretching circuit that can accurately determine the duration even when the duration is long.

[Main points of the present invention] The present invention improves this, and includes a bistable flip-flop circuit that enters one stable state by an input pulse, and a bistable flip-flop circuit that enters one of the stable states when the flip-flop circuit is controlled by INK. An oscillation circuit that generates a signal with a constant frequency for a certain period of time, and an output signal of this oscillation circuit that is frequency-divided by a predetermined frequency division ratio, the frequency-divided output is fed back to the flip-flop circuit, and this frequency-divided output is sent out. The flip-flop circuit may include a frequency dividing circuit configured to be in the other stable state, and an output signal of the flip-flop circuit may be guided to an output terminal.

[Explanation based on examples]

FIG. 2 is a block diagram of a circuit according to an embodiment of the present invention. The input pulse applied to the input terminal IK is applied to the set input 8 of the bistable flop circuit 20, and its output q is led to the output terminal 3 and branched to 4K to control the oscillation circuit 6. In this example, when the output q of the flip-flop circuit 2 is at the NO level, the bias voltage of the oscillation circuit 6 becomes active and sends out an output at a constant frequency. This output is applied to the frequency divider circuit 7 to be frequency-divided by y, and the frequency-divided output is fed back to the reset input of the flip-flop circuit 2.

3rd IlIK shows a time chart explaining the operation of this circuit. Namely, when the input terminal IK input pulse comes, the 7-rip-flip circuit 2 is set by the input terminal IK, and its output QK is the signal 1 sent out. . At the same time, the oscillation circuit 6 becomes operational and sends out a repetitive pulse 0 of a constant frequency.

When this is counted M times by the frequency dividing circuit 7, the output K11
m pulses D are sent out, and the flip-flop circuit 2 is reset. As a result, a short input pulse given to input terminal 1 is extended to output terminal 2 and output pulse 1 is extended to output terminal 2.
Sent as .

This circuit is entirely composed of digital circuits, and the 0 oscillation frequency determined by the duration of the output pulse, the oscillation frequency of the oscillation circuit 6, and the frequency division ratio of the frequency divider circuit 70 is determined by an inexpensive configuration (for example, OR The 0 frequency division ratio, which can be selected and designed arbitrarily, from high-precision and expensive configurations (using a constant temperature bath in a crystal oscillator), can be digitally set as many times as necessary.

The operation of the oscillation circuit 6 may be controlled by controlling the output gate using a control signal, without necessarily controlling oscillation and stopping. In this case, since the oscillation circuit 6 can be operated continuously, the stability and accuracy of the oscillation circuit 60 are increased.

[Explanation of effects]

As described above, according to the present invention, it is possible to obtain a circuit in which the duration of the output pulse can be set arbitrarily and accurately from a short time to a very long time. Since this circuit does not require a large capacitor or the like, it can be constructed with a small m.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional circuit. FIG. 2 is a block diagram of a circuit according to an embodiment of the present invention. FIG. 5 is a time chart for explaining the operation. M~D is the 2nd I
The waveforms of points M to D indicated by ilKX marks are shown. 1--Input terminal, 2--Bistable flip-flop circuit, 3--Output terminal, 4--Integrator circuit, 5--Threshold circuit, 6--Oscillation circuit (output of flip-flop circuit) ), 7... frequency divider circuit. M1 Figure yl 2 Figure D□8-11-[

Claims (1)

[Claims] (1) A bistable Aritz flop circuit that enters one stable state by an input pulse applied to the input terminal, and a signal of a constant frequency that is controlled by this 7-lip flop circuit for the time that this Aritu flop circuit is in one of the above stable states. The output signal of this -oscillation circuit is divided by a predetermined frequency division ratio, and the divided output is fed back to the above-mentioned Treetub flop circuit, and when the ζO frequency division output is sent out, the above-mentioned Tritub flop circuit and a frequency dividing circuit configured to be in a stable state, and an output signal of the flip-flop circuit is guided to an output terminal.