JPS58129679A - Picture information display - Google Patents

Abstract

PURPOSE:To enable effective use of the display area of a display section, by setting the reduction ratio of a size changing circuit basing on correlation between the size of an original and the display area of the display section. CONSTITUTION:When an original 8 is set to a two-dimensional scanning device 7, picture information on the original 8 is stored successively in a page buffer memory 5. At this time, the size of the original is supplied to CPU 2 and stored in its RAM. On the other hand, when picture information for one unit is stored in the page buffer unit 5, the CPU 2 reads out the size changing ratio corresponding to detected size of the original and set it to a size changing circuit 14. By this way, picture information in the page buffer memory 5 is reduced by the size changing circuit 14, and stored in a refresh memory in an interface for display 15.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention stores image information such as documents in a storage device, and retrieves and reads required iikigI information from among the various image information stored in the storage device as needed;
The present invention relates to an image information display device for an image information storage and retrieval device that outputs the image in a visually visible manner.

[Technical background of the invention and its problems]

Recently, image information such as documents, etc., which is generated in large quantities, can be processed using optical
The information is read by dimensional scanning, and this read nine-stroke information is stored in a storage device, such as an optical disk device, and
An image information storage and retrieval device has been developed that searches for desired image information as needed from among the various image information stored in this storage device, outputs it in a format that can be visually viewed on a hard copy device. and has been put into practical use.

In such an image information storage and retrieval device,
In order to deal with the difference between the reading speed and the storage speed or the difference between the reading speed and the recording speed, the image information for 91 units of reading (-Kaiben) or the image information for one unit of reading is temporarily I am trying to store it in memory.

Mapeno ζ can display image information in the family memory on a monitor.

By the way, as shown in FIG. 1, the page bar has a storage area of 2800 lines of Noah memory, whereas the fresh memory in the display interface has a storage area of 1024 bits x 70 lines.
There is only a storage area for the G' line, so it is impossible to display all the image information in the pager and file memories all at once on the CRT display gray.

Therefore, in the past, a size conversion circuit was provided in the display interface to reduce the image information successively output from the pager and file memory to 1/4 and store it in the fresh memory, as shown in Fig. 2 (a). In this way, all the image information in the page buffer memory can be displayed on the CRT display at once.

However, in this case, the reduction ratio is constant regardless of the size of the image information, and the size of the image information displayed on the CRT display varies. There was a drawback that the display area on the ray was not used effectively.

[Purpose of the invention]

This invention was made in consideration of the above circumstances,
The objective is to provide an excellent image information display device that can effectively utilize the display area.

[Summary of the invention]

The present invention reduces image information using a size conversion circuit, stores it in a refresh memory, and displays the image information in the refresh memory on a display unit, in which image information #4i! By setting the reduction ratio of the size conversion box based on the correspondence between the size of the original and the display area of the display unit, it is possible to convert the image information to a constant size and the entire image. It is also O if the display area of the display section is to be displayed all at once.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In Figures 1 and 2, there is an IFi main controller, a CPU 2 that performs various controls, each side file set (optical disk mounting platform to be described later), and operational information for managing various files (optical disks). Stored management information ml storage, for example 70. A B-disc device 3, a title memory 4 for temporarily storing title information successively outputted from a source disk device 9, which will be described later, and a storage area (2048 bits) corresponding to image information for at least one unit (manuscript - one piece). , hX2800 lines), a file memory 5, and a mother data generator 6 in which /4' turn information such as characters and symbols are stored. i, 1 is a reading device, for example a two-dimensional scanning device;
By scanning the manuscript (text 4k) 8 two-dimensionally, the manuscript 8
A video signal corresponding to the above image information is obtained. 9
The image information read by the two-dimensional scanning device and the image information created by the main controller 1 are stored in the dedicated storage area of the optical disk. It is stored sequentially.

A keyboard 10 is used to input a unique title and various operation commands corresponding to the image information. 11
A hard copy device is an output device, and outputs image information read by the two-dimensional scanning device 2 or image information read from the optical disk device 9 as a hard copy 12. Reference numeral 11 denotes an output device, which is a ζ-shaped image display device, which consists of a size conversion circuit 14, a display interface 15, a cathode ray tube display device (hereinafter referred to as CRT display) 16, etc. This is for displaying image information read from the optical disk device t or image information read from the optical disk device t.

Therefore, 1 disk device S1 type file memory 4, pager, file memory 6, main turn generator 6, two-dimensional scanning device a11, optical disk number register, keyboard 1#, hard copy device wit, v-ize conversion circuit 14
, display interface 15 are each connected to a data bus 20 from the CPU 2. Also, title memory 4, (-no puffer memory 5, pattern generator 6)
．． The two-dimensional scanning device 1, the optical disk device 9, the hard copy device 11, the size conversion circuit 14, and the second display interface 15 are each connected to the image path 21,
Information is transferred to each other.

Here, FIG. 3 specifically shows the two-dimensional scanning device 1. As shown in FIG. That is, 31 is a paper feed tray, and the originals set on this tray 31 are taken in by rollers 32 and J.
It is taken into the main body by J, and further transferred to the conveyor row 2ss,
ss onto the document table (glass plate) 34.

The original that has passed through this original table j4 is transferred to the transport row 235.
35 and discharge loaf 36. , IIg, the paper is discharged onto the paper discharge tray S7. A pair of exposure runs f38.degree. The image is then projected onto the CCD line sensor 4JK via the projection lens 40. In this way, a video signal corresponding to the image information on the document can be obtained from the line center t41.

In addition, a photocoupler consisting of a round light emitting diode 42 and a phototransistor 43 for detecting the document to be captured is provided near the capture roller 32.degree. 32, and also for detecting the size of the document being captured. Round light emitting diode 44m (44b, 44@.

44d) and phototransistor 46m (41b
.

45@*414) are arranged.

4(a) and 4(b) show the structure and operation of an operation control circuit based on the output of the phototransistor 41. That is, the output of the phototransistor 43 is supplied to the 31st timer 41 via the inverter 46. The first timer 4i outputs a drive signal No. 16 for operating the rollers and runnos 38, 38 for a certain period of time after the leading edge of the document is detected. The second timer 41 outputs a reading start signal for operating the line sensor 41 a predetermined time after the leading edge of the document is detected. The third timer 48 is configured to output a reading end signal for stopping the operation of the line sensor 41 after a predetermined time after the leading edge of the document is detected. Also, Figures 5(a) and (b) are from the above-mentioned 7 Ototora/Nosta 4fa (4rb, 4i book, 4
sd) and the configuration of a size detection circuit based on its output. That is, each light emitting diode and its corresponding phototransistor 451° 41b, 41e, 41d are arranged in a direction perpendicular to the document conveyance direction.
are arranged at regular intervals, and the AND circuit 49.
50, 51.51, the M1 detection value number sB4 detection signal, A4 detection signal, and BI detection (11M) are obtained, respectively.

Here, we will briefly explain what kind of operation is performed in the above configuration.

When a document 1 is set on the two-dimensional scanning device 1, the document 8
The above image information is read and stored sequentially in the page buffer memory 5. At this time, the document size detected by the two-dimensional scanning device 1 is supplied to the CPU J.
It is stored in RAM in UJ. When one unit of image information is stored in the page buffer memory 5, C
The size conversion rate (reduction rate) corresponding to the detected Kuhara bucket size is read from the ROM and set in the size conversion circuit 141fC. In this way, the image information in the penopa memory 5 is reduced to a predetermined size by the size conversion circuit 14 and stored in the refresh memory in the display interface 1j. Then, the image information in the reflex memory is displayed on the CRT display gray 16.

Further, when image information is read from the optical disk device 9,
The read image information is sequentially stored in the peno pufferme 7. At this time, the document size information previously included in the index information corresponding to the image information that is successively issued is supplied to the PIJ 2 and
Stored in M.

When one unit of image information is stored in the page buffer memory 5, the CPUJ reads the size conversion rate (reduction '4) corresponding to the stored original size information from the ROM and transfers it to the size conversion circuit. Set to 14. Thus, Penopa.

The image information in the file memory S is reduced to a predetermined size by the size conversion circuit 14 and stored in the refresh memory in the display interface 15. Then, the image gI information in the refresh memory is displayed on a CRT 7" frame with 1σ.

Next, the above-mentioned size conversion circuit 14 and display interface 15 will be explained in detail.

First, FIG. 6 shows the size conversion circuit 14.

That is, 1li of 12 inches of page buffer memory 6
i-image information is supplied to data input terminal 400. In this case, 12 inches of image information consists of 2048 pixels. Image information dRAM 40J and 6 pits are supplied to the terminal 400.

It is supplied to child circuit 406. RAM 401 is 2 x 1
The address is specified by the output of the counter 413. So, 5 RAM 40
1 to 405 and seven child circuits 406 to 412 are provided. These RAMs 40J to 4 (15 and 406 to 412) are all supplied from the main clock generator 414 via the signal path shown by the solid line and the signal path shown by the two-dot chain line. The signal path shown by the solid line is used when working as a reduction circuit, and the signal path shown by two-dot chain line is used when working as an expansion circuit.

Under the address control of the counter 433, the image information of the first line of 2048 digits is stored in the first RAM 4.
#J K stored 0 Then, when the first bit of the second line of image information is supplied to RAM 401, R
The first bit of the first line image information stored in AM 401 is read therefrom and double-checked in latch circuit 406.

Meanwhile, the first bit of the second line is stored in memory location klJ of RAM 40J.

The second bit of the second line is then stored in the RAM 40J, and the second bit of the first line is latched into the child circuit 404 in sequence from there.

At the same time, the first bit of the first line loaded into the latch circuit 407 is read out to the RAM 402 and stored therein. In this way, the end of the second line (2048th)
, the first line of image information of 2048 bits is shifted to RAM 402. In total, 15 each of 2048 pits! The in-image information is sequentially shifted in RAMs 401-405. lastly,
The image information of the 1st line to the 5th line is stored in RAM.
The first bit of the image information of each of the 12th to 5th lines stored in 405 to 401 is loaded into the latch circuit 406, and at the same time the first bit of the 6th line image information is supplied to the terminal 400.

The signal is supplied to the latch circuit 407 along with the signal.

When the second bit of the 62nd input 5 is supplied to the terminal 400, it is output to the child circuit 401, and the first bits of the 12th input to the 6th line are supplied to the next latch circuit 40g. and each @2 bit of the 12th in to 6th line is 2. 2 is checked in the child circuit 4or. Similarly, when the seventh bit of image information of the sixth line is supplied to the terminal 400, the first bit of each of the first to sixth lines is latched in the child circuit 412, and the second The bit is latched into the latch circuit 41, the 1s3 pit is filled into the latch circuit 410,
4th Bi, Towel.

The fifth pit is latch circuit 4.
88, and is latched to the sixth pin 401. Therefore, latch circuit 401
~412 and 9 bits each! When rearranged in the array, the original image is reproduced as a one-dot image as shown in FIG. In Figure 9, black
The white bit represents 1 pin, and the white bit represents 0 pin.

Therefore, local image information of 6 pins, 6 lines (in the x direction) x 6 lines (in the y direction) is stored in the latch circuits 405 to 41.
2 to the operation ROM 4'J j.

Two addresses 416 and 417 and two latch circuits 4
18, 419, a comparator 420, and a counter 413 constitute a distance calculation circuit 430 in the X direction, and two adders 4
21.42. ? , two latch circuits 423 and 424, a comparator 425, and a counter 426 constitute a distance calculation circuit in the Y direction. These distance calculation circuits 43o.

431 is used for rounding to calculate the position of an image dot whose size has been converted in the X and Y directions.

The size conversion (enlargement, reduction) rate setting data in the X and Y directions supplied from the CPU 2 is sent to the adder 416.41.
7.421 and 422. In FIG. 6, reduction rate data is shown as an example. The integer part of the reduction ratio is supplied to adders 4xe, 41j and decoder 421, and then to its fractional division adders 411, 422. Adder 4 J 6 , 411.421 , 4:1
2 output goes, child circuit 4111, 419, 423°42
4 respectively. The outputs of the child circuits 411 and 418 are respectively supplied to one input terminal of the comparators 420 and 411, and the input side of the adder 416.4:II is provided with a feed pad,
The other side of the comparator 420° 425 is the counter 4
It has inputs from 13,426. U, child circuit 419.
The outputs of 423 are fed to the input sides of adders 417r and 4110, respectively.

3 bits of fractional part output data of circuit 430 and circuit 43
The 3 pins and 3 pins of the 10th fractional output r-1 are taken out from the respective latch circuits 419 and 424 and supplied to the arithmetic ROM 4J5 as address designation signals. Arithmetic ROM 4
The nine output data read from Jj is supplied to the input side of comparator 431, and the other end of comparator 482 is supplied with slice level data obtained from slice level data oscillator 481. Comparison-412 match signal is Furi, Noah 0
．． and ff −)
The output of 4j Is is supplied to the black terminal CL of the 7-rig flag. The coincidence output XC0M of the comparator 420 is supplied to one input terminal of the ANDY-TO 435, and the input YCM from the Hiyuki return 425 is supplied to the other input terminal.

Here, the operation of such size conversion circuit 14 will be explained in detail with reference to FIG. 8. Assume that the reduction rate specified by CPUJ is 1/4.5. In this case, the integer part of the reduction ratio is 4, while the fractional part is 0.5.

Digitally formed numerical data are each added by an adder 416.4
11 and 421.422.

In FIG. 8, the image dot position on the original image is specified by the symbol "X", whereas the image dot position on the size-converted image is specified by a black dot.
) is defined by (pl, ).

The image at position (I, J) on the reduced image is (Q, ,
, ) is defined. The distance between two adjacent image dots on the original is defined as 0.Then, the distance between two reduced dots on the original is equal to the reduction ratio Rr.

L = R.

In this case, the constant value is set as 4.5. When the LXL region with center position Q1,1 is designated as S,
The average gray level of S is the image color (P) belonging to region S.
, , j) exists or not. Defining the distance between each original position P t , r and the transformed position as ri, j, the average gray level φ
11. The weighting factor for calculating 7 actors α1. j is determined to be inversely proportional to the distance r5j. After a while,
Factor αi, J to Q. , set as 1 at position J,
When set as 0.5 at nine positions separated by I4/2, the factor αi,J can be expressed as α = 1−H×r 1 , J = 1−Moi,j. Therefore, it becomes an average gray level.

Then, the transformed image Q, , is obtained by using a predetermined slice level θ.

Therefore, the integer part 4 of the reduction ratio supplied from CPUj
is supplied to latch circuit 418 via adder 416. When the content of the counter 413 becomes 4, the match signal XC0
M is sent out from the comparator 420, and
19 and AND gate 435. On the other hand, the fractional part 0.5 is sent to the latch circuit 419 via the adder 411.
I'm going to get fucked. Therefore, when the signal XC0M is supplied to the 2° child circuits 418 and 419, 0.5+0,5=
An operation of 1 is performed in adder 411, and a carry of 1 is supplied to adder 41#. Therefore, the operation 4+4+1-9 is performed in the adder 416, and the new r-data "9" becomes 2.
．． It is set in the child circuit 411. At this time, the counter 41
When the content of 1 becomes 9, the output XC0M is 0 obtained from the output of the comparator 420. Then, 9+4=13 becomes 2. Child circuit 4
It is set at 11. For output XC0M, counter 413 is 1
You can get it by multiplying by 3. At the time of jin, the operation of 13 + 4 + 1 is performed in the adder 41g, and the new data @ 18'' is 2
．． It is set in the child circuit 418.

In this way, the content of the counter 418 becomes "4,9°13.1".
8.22, 27. . . ”, one output XC0M is obtained from the comparator 420. This output XC0M is supplied to one output of ANDr-)4:IJ.

The same operation as circuit 430 is performed in circuit 411 as well. Output YCOM indicates that the content of counter 42# is "4".
．． 9, 13, 18, 22.27°...1 for every 1
Comparison@415 feeds the other input of ANDDART 435. When both inputs XC0M and YCOM are fed to AND gate 435, the output is FRI,! Frotsuno 434
Kuro.

is supplied to the terminal. At this time, when the output level φI, J matches the output level of the slice level generator 433, the output from the comparator 432 is D
The output Q of the black dot is supplied to the terminal as shown in Figure 8.
,, 1 is 7 litsugu floats! 434.

In the enlargement operation, for example, an enlargement rate of 0.5 is
2 to adders 416, 411, 421 and 422. In this case, the number of Ql, J is twice the number of P t, j], and the picture information is expanded twice.

Next, FIG. 9 shows the display interface 15. 60 is reflex, shi, memory, 1024 bits,
It has a storage area of 1,400 y (in the x direction) x 1,400 y in (in the y direction). (The CRT display 16 has a display area of 1024 pits x 700 lines), 61 is 16
The image information reduced and supplied by the size conversion circuit 14 is refreshed once every 16 bits in the bit register.
It is the turtle that supplies the memory 60. 62 is a selector,
This selects the output of the 16-bit register 61 or the 74-turn information from the no-turn generator 6. g3 is a write address counter, which temporarily holds the drawing information write start address supplied from the CPUJ, and converts the error to the size conversion circuit 14 (Fri, f70/4).
S4) to 1716 counter 64 and AND circuit g1
The black and white signals supplied through the account account,!
I'm going to go ahead and do it.

%1) 60 (This is the turtle that specifies the DX and Y direction addresses. This write address counter aS is set at the lower right end of memory #0 at the end of writing the image information. /l turn information write address corresponding to the specific area is supplied from CPU J. In this case, the other input terminal K of the AND circuit 6J #1 CPU J
A ``0'' signal is supplied from the address counter #JK.

Reference numeral 66 denotes a CRT controller, which consists of a counter 67, an address register 68, a 700 line detection circuit 69, etc., and when reading out image information from the refresh memory 60, controls the CRT controller in the X and Y directions of the refresh memory 60. It is used to specify addresses. here,
The counter 67 receives the 1/16 counter 1 from the oscillation circuit 70.
1/
It consists of a 64 force counter 6Fm and a counter grb that performs a carry count of this counter 611.
The contents of 1a are set as the X-direction specified address, and the counter 61b
The content of is the Y-direction designation address. Further, the address register 6a holds a read start address (line address) supplied from the CPUJ. The 700 line detection circuit 69 has a counter 67
Detects whether 1b has counted @700” and @
If 700= is counted, the start address of the address register 6# is newly set in the counter 61b. A selector 72 selects either the Y direction designated address of the address counter 630 or the counter gyboy direction designated address during writing and reading. FJ is a selector that selects either the address counter 1 sox direction designation address or the counter 6Fa (DX direction designation address) during writing and reading. 14 is a 16-pin register; The output of the oscillation circuit 1o is clocked by the 16-bit image information read from the
It is output serially as a signal. 10 is a key setting circuit, which connects the CRT controller 6σ to C
Ridis! Horizontal synchronization signal Hsy supplied to Ray IC
m.

A cursor video signal corresponding to a predetermined cursor (frame) is generated in synchronization with the vertical synchronizing signal Vsym* and the p and p signals from the oscillation circuit 10. However,
The cursor video signal generated from the cursor setting circuit 80 and the video signal output from the 16-bit register r4 are supplied to the CRT display 16 via the L-OR circuit 200.

Here, FIG. 1θ shows the cursor setting circuit 80. In FIG. 1θ, reference numeral 81 denotes an X-direction cursor memory, which holds position information on both sides of the cursor in accordance with write code information J from the CPU 2. 8
Reference numeral 2 denotes a Y-direction cursor memory, which holds position information of the upper and lower sides of the cursor, respectively, in accordance with the write code information @J from the CPUJ. Reference numeral 81 denotes an X-direction address counter that counts the horizontal synchronization signal Hsyne supplied from the CRT controller 66. 84
is the Y-direction address counter, and the CRT controller 66
This is to count the vertical synchronization signal Vsyae supplied from. 85 is a decoder, and when the contents of the counter 83 match the position information on both sides, the logic is ``1-4''.
No. 11 is output. 1g is a decoder which outputs a logic ``''1m1m signal when the contents of the counter s4 match the position information of the upper and lower sides, respectively.
'i, ms is T-furiraguro,! , 89 is an OR circuit,
901.

mol, mos are AND circuits, W is pulling signal, Cv
is the cursor video signal. On the other hand, number 1! In the diagram? 92 is a cursor key provided on the keyboard 10, and 93.94°91, #i is a movement key, which produces a movement/f pulse while being pressed. 91 is a round movement key for moving the cursor and 9 the display area of the CR display 160 corresponding to the image information in the refresh memory 16 to the upper left corner. 91 is an enlargement key, and 9# is a reduction key. Therefore, FIG. 12 shows what kind of operation is performed in the cursor setting circuit go.
aHorizontal synchronization signal Hsyt+@1. Noodles are vertical synchronization signal Vi
yw+*, Sake is the output of lever 8J, d is the output of depu-〆IC, ・ is the output of AND circuit 901, f is T-
Furi, Zofro, ga1 output, g is T-7 Ritsuguflotsu! 81, h is the output of AND circuit 901, and fish is the output of OR circuit #-.

In such a configuration, how image information is displayed will be explained.

When a document 8 is set on the two-dimensional scanning device 1, image information on the document is read and the size of the document is detected. Then, the read image information is stored in the page storage memory 5 in a size corresponding to each size, as shown in FIG. At this time, if the document size is 84, the CPUJ sets the reduction rate of the size conversion circuit 14 to 1/4. If the mode is 4, the reduction rate is 1/
If 3.3, n, the reduction rate is 1/2.7, A.

In that case, the reduction rate is set to 1/2. In this way, the image information in the pager 5 is reduced in size by the size conversion circuit 14, and then stored in the memory 60. When the image information is stored in the refresh memory 60, the CPUJ reads the character/main turn corresponding to the original size of the image information from the parable turn generator S, and stores it in a specific area of the image information in the fresh memory 60. Add.

Therefore, Iris 14 (a) (b) (,) (d)
As shown in , the entire image information is displayed on the CRT display at a constant size, regardless of the document size. ray 16, and the display area of the CRT 5" chair! ray IC is utilized to the maximum extent possible. Moreover, in this case, the displayed image information is rounded with the document size added to the lower right part. , the original size of each image information can be easily recognized by K1m.
And if manuscript 1 is used in landscape orientation,
Image information is shown in Figure 11115 (a) (b) (@) (d
), the display area can be used more effectively without being displayed over the entire display area of the CRT.

and ζro, in this general iii* information display, rounding, which increases the reduction rate to a certain extent for the image information,
There is a problem with resolution. However, keyboard 1el
If you perform the specified operation on C, B4 size image information will be reduced to a reduction rate of 1/2, B4 size image information will be reduced to a reduction rate of 1/1.7, and B4 size image information will be reduced to a reduction rate of 1/1.7. 1/1
．． At step 3, the AI size image information is each reduced at a reduction rate of 1/1 and stored in the refresh memory 60. In this case, the CPUJ performs the control shown in the flowchart in FIG. is displayed on a CRTf (16 stripes).

That is, as shown in FIG. 17(a), the image information of the upper half area (solid line in the figure) of the refresh memory 60 is displayed. Further, the CPU J sets the address of the cursor S in the cursor setting circuit 80 as shown by the dashed line in FIG. When the cursor key 96 is turned on in this state, the CPU 2 increments the contents of the address register 68 of the CRT controller 6C by, for example, +10. In this way, each time the cursor key 96 is turned on, the display area for image information in the refresh memory 60 sequentially moves downward as shown in FIG. 17(b) (@). In this case, the display area and the cursor S There is no change in the corresponding position of cursor S. After that, when the Y-direction start address reaches -700'', CPU J rewrites the Y-direction address of cursor S in cursor setting circuit 10 every time cursor key 96 is turned on. , In this way, each time the cursor key 96 is turned on, FIG. 17(d) (・)
As shown in the figure, the cursor S moves downward.

From this state, you can turn on the cursor key 9S.If you turn on the cursor key 95 in the state shown in FIG. 19(a), the cursor 8 will move to the right because there is no movement range in the display area. This results in the state shown in FIG. 19(b). Sara Ksj
If you turn on cursor key #4 in the state of Izo diagram (a), only the cursor S will move to the left and the 920 diagram (b) will appear.
It becomes o state.

If the enlargement key 9I is turned on in such a display state, the image information within the cursor S is enlarged and newly displayed. 9. If you turn on the reduction key 99, the original display will be made.

In this way, by specifying movement of a certain area for the image 11 (# information) in the refresh memory 6o, the image information within that area can be displayed immediately. There is no need to continuously read data from the memory, and the display speed can be greatly improved.Moreover, the display can be performed using the above movement specification, ii!ii
The information reduction rate for large information is 7, and it only needs to match the storage capacity of the memory 6o, and the reduction ratio can be made larger than when matching the display capacity of a CRT display. is easy to recognize.

Moreover, since the designation of movement of a fixed area is given priority over the movement specification of the zoomer and f-area, a single operation mechanism can perform operations for each movement specification, which is extremely convenient in practice. It is.

In addition, in the above embodiment, priority is given to specifying movement of a certain area, but priority may be given to specifying movement of the cursor.In addition, the present invention is not limited to the above embodiment. Of course, various modifications can be made without changing the gist.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an excellent image information display device that can effectively utilize the display area of the display section.

[Brief explanation of the drawing]

Figure 1 is an overall schematic configuration diagram of an image information storage and retrieval device according to an embodiment of the present invention, Figure 2 is a detailed configuration diagram of Figure 1, and Figure 1Ia is a specific diagram of a two-dimensional scanning device. Configuration diagrams, FIGS. 4(a) and 4(b) show the operation control section of FIG. 3, (a) is a circuit configuration diagram, (b) is a time chart,
5(a) and 5(b) show the size detection section of FIG. 3, where (a) is a plan configuration diagram, (b) is a circuit configuration diagram, and
The figure is a block diagram specifically showing the size conversion circuit in an embodiment of the present invention, Figure 97 is a diagram for explaining the operation of #I8 #611, and Figure 9 is a display in an embodiment of the present invention. Fig. 10 is a block diagram specifically showing the cursor setting circuit in Fig. 9, Fig. 11 is a block diagram of the cursor keys, and Fig. 12 explains the operation of Fig. 10. The time chart shown in Figure 13 shows the page buffer memory and the various sizes of It! 11 Configuration diagram showing correspondence with law information, Part 1
Figure 4 (,) (b) (c) (d) and Figure 15 (,
) (b) (c) (d) are diagrams showing the overall display state of image information in the non-embodiment of this invention, FIG. 16 is a flownayat showing display control in the same embodiment, and FIG. 17 (a) (b) (e) (d) (fist), Figure 18 (a) (b) (e) (d) (@), Figure 19 (a) (b) and Figure 20 (&) (b) are the same. It is a figure which shows an example of image information, a cursor, and a display in an Example. 2...CPU, 5...Page buffer memory, 6.
...Mother turn generator, 13... Image information display device, 14... Size conversion circuit, 15... Display interface, 16... CRT display, 60...
・Refresh memory, 80... cursor setting circuit,
92...Cursor key. Figure 3 Figure 4 (b) Calligraphy front door Shibu Takuryo No. 1 Figure 5 (a) (b) Figure 13 Figure 14 (a) (b) (c) (d) (d) ( a) (b) (a) (b) δ “0 Fig. 19 (a) (b) ”60 Fig. 17 Fig. 18 Fig. 20 (a) (b) Book O

Claims (1)

[Scope of Claims] (Li) A size conversion circuit for reducing the supplied image information, a fresh memory for storing image 1H information obtained through the size conversion circuit, and image information in the refresh memory. and a control means that has the supplied image information and sets the reduction rate of the size conversion circuit based on the correspondence between the size of the companion document and the display area of the display section. (2) The image according to claim gx, characterized in that the image information displayed on the display section has document size information added to a specific area thereof. Information display device.