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JPS58119060A - Fault recovery detector for central processing unit - Google Patents

Fault recovery detector for central processing unit

Info

Publication number
JPS58119060A
JPS58119060A JP56215125A JP21512581A JPS58119060A JP S58119060 A JPS58119060 A JP S58119060A JP 56215125 A JP56215125 A JP 56215125A JP 21512581 A JP21512581 A JP 21512581A JP S58119060 A JPS58119060 A JP S58119060A
Authority
JP
Japan
Prior art keywords
counter
processing unit
value
central processing
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56215125A
Other languages
Japanese (ja)
Inventor
Yasusuke Katagiri
片桐 庸介
Osamu Yoshida
美田 修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56215125A priority Critical patent/JPS58119060A/en
Publication of JPS58119060A publication Critical patent/JPS58119060A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751Error or fault detection not based on redundancy
    • G06F11/0754Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03GELECTROGRAPHY; ELECTROPHOTOGRAPHY; MAGNETOGRAPHY
    • G03G9/00Developers
    • G03G9/08Developers with toner particles
    • G03G9/087Binders for toner particles
    • G03G9/08702Binders for toner particles comprising macromolecular compounds obtained by reactions only involving carbon-to-carbon unsaturated bonds
    • G03G9/08735Polymers of unsaturated cyclic compounds having no unsaturated aliphatic groups in a side-chain, e.g. coumarone-indene resins

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To measure the frequency of automatic recovery of a CPU at distance through the operation of a watch dog timer. CONSTITUTION:The watch dog timer WDT detects abnormal operation of a program and when an interruption to the central processing unit CPU is caused, a counter CNT counts its signal. For this purpose, the frequency of the occurrence of program abnormal operation is commanded by a central controller CC and then the counter CNT value of a subordinate station SS is reported immediately by regarding the modulator and demodulator of each station as the main part of a communication device. Further, a device for checking the variation value of the counter CNT per unit time is provided in the CPUCC of a master station MS. Then, the value of the counter reported at intervals of unit time is compared with a preset value and when the reported value is greater, an alarm is generated.

Description

【発明の詳細な説明】 11?発明の技術分野 本#、#4は中央処理ik皺が動作中プログラム1:関
する異常動作が発生し、目動作出した「!1数ケ計掬す
るa會に関する。
[Detailed Description of the Invention] 11? Technical Field of the Invention Books # and #4 relate to a meeting in which an abnormal operation related to program 1: occurred while the central processing unit was operating, and an eye movement occurred.

Q1技術の背景 システムの動作プログラムが止常(二動作しているかど
うかな監視する方法の一つに〜オツチドッグタイマ19
を便用することが行なわれ又(する。
Q1 Background of the technology One of the ways to monitor whether the operating program of the system is stopped (2) is running - Otsuchidog timer 19
It is practiced to make use of (to do).

システムがノイズ等のため偶発時(二全生しだ外電が原
因でプログラムの1Ih71:が起ったとぎ装置を自動
復1日さすることがでさる。11図(二e略的に示すウ
ォッチドッグタイマC:ML’て中央処理装@ opt
rのアクセスによりリセットされるタイマチ1Aン設け
ている。
If the system is accidentally damaged due to noise, etc. (1I h71: of the program occurs due to an external power line), the sharpening device can be automatically restored for 1 day. Dog timer C: ML'te central processing unit @ opt
A timer 1A is provided which is reset by access of r.

タイマチ讐のリセットはプログラムの通常処瑯ルーチン
の中で行なわれ、9セツトされる場合の流れ1を第2図
に示す。しかしプログラムカβ異常動作を始めた場合は
タイマをアクセスしてリセットすることがない定め、予
め設定した時間を超えるので、そのときタイマは中央処
理装置1070に割込みを上げ、ζ11込処理が行なわ
れたことにより、動作な書出さする。
The reset of the timer is carried out in the normal processing routine of the program, and flow 1 when the timer is set is shown in FIG. However, if the program begins to operate abnormally, the timer will not be accessed and reset, and the preset time will be exceeded. At that time, the timer will issue an interrupt to the central processing unit 1070, and ζ11 processing will be performed. By doing so, you can write out the file in a working manner.

■質素抄術と問題点 ウォッチドッグタイマ舎工装置lン蕉入局に設置しであ
る場合などシステムを自動的に運転さゼである所では有
効であるがプログ2ムの異常動作発生回数は記録されな
い。即ちグログラムが華走しタイマにより自*+*旧す
ることが、プログラムに一寸した欠陥が元来あって発生
していることが、偶発的に起ったためで特に原因がない
ことが判断できない。
■Frugality and problems Watchdog timer construction equipment is effective in places where the system is not operated automatically, such as when installed in a station, but it records the number of times abnormal operation occurs in the program. Not done. In other words, it cannot be determined that the fact that the program runs out of date and becomes obsolete due to the timer is due to an accidental occurrence due to an original defect in the program, and that there is no particular cause.

+41発明の目的 本発明の目的はウォッチドッグタイマが動作し、中央処
理装置が自動復旧した回数ン離れた場所において針側で
さる装&な提供すること1:ある。
+41 OBJECTS OF THE INVENTION An object of the present invention is to provide a system for monitoring the number of times a watchdog timer operates and a central processing unit automatically recovers on the needle side at a remote location.

+51発明の構成 本発明の構成は中央部f!!装置からのアクセスにより
リセットされるタイマを設け、所定特間以円C:リセッ
トされないとき中央処理装置に対し割込みン上げるウォ
ッチドッグタイマと、lf9オッチドッグタイマが割込
みを上げた回数を計数するカウンタと、該カウンタの匍
ケ上位装置へ連絡する通信装置とを具−することである
+51 Structure of the Invention The structure of the present invention is the central part f! ! A timer that is reset by access from the device is provided, and a watchdog timer that raises an interrupt to the central processing unit when it is not reset after a predetermined period of time, and a counter that counts the number of times the lf9 watchdog timer raises an interrupt. , and a communication device for communicating with the upper level device of the counter.

−発明の実施例 第3−は本発明の一実施例1示すブロックηであって、
親局Meには中央制a曹tiICC,メモ5yMe’W
i遍列変攬装置8ρ、り′僧副器シODIM、入出力制
御装置Iooを設け1表示袈負D8Pな接続している。
-Embodiment 3 of the invention- is a block η shown in Embodiment 1 of the invention,
Main station Me is central system asotiICC, memo 5yMe'W
A parallel transformation device 8ρ, an auxiliary device ODIM, and an input/output control device Ioo are provided and connected to each other.

子局S8は親局M8と回線〒Lで′J#続され、中央処
理製&0Pt7.メモリMM、[並列W戸装置Vア、資
復1器シ○DI輩。
The slave station S8 is connected to the master station M8 by line 〒L, and is connected to the central processing unit &0Pt7. Memory MM, [parallel W door device V a, recovery 1 device S○DI guy.

入出力制am置roe、ウォッチドッグタイマWDテ、
カウンタCWTとその1sfiAIPyt設け、センナ
118を接続している。カウンタ(’NTにはクロック
入力端子c′L工’s t ’Ws fA一端子Voo
、プリセットイネーブル端子7B!、カウンタ帥出力端
子0テ0が設けられているnなおこのカウンタ0)fテ
は子局の中天処理装置IILcp’ryが動作てるソフ
トウェアによってはカウント餉ンt!+込むことができ
ない11#成としておく。それにプログラム暴11IL
#Pにカウンタの111 V 4に廉さnないようにす
るためである。なおりウンデON〒の電源1は蓄電池等
−:よるバックアップ形式なとり1wM用電源の停電時
においてもカウンタOMTの量は保持される構成として
おく。そしてカウント噛をV)期化することを工、動作
電源な立上げたとき、長期停電でバックアップ電源が継
持できなくなってから醤電なさせるときにのみ行なうよ
うにして1通常はエンドレスにカウントして行くのその
ためウォッチドッグタイマWDデが従来の方法でプログ
ラムの異常動作を検出し、中央処理装* cptrに割
込みを上げたとき、カウンタ01丁はその信号をグロッ
クとしてカウントして行く。そのためプクグラム異常動
作の発生した回数は親局M8の中央制御装@00が指令
すると各局の習醤胸装置を通信装置の主要部として子局
meのカウンタCNT偉を置ぐ軸普する。更CHIN輩
Bの中天制御装置00内に設ける装置として、単位#F
間当りのカウンタOw〒の萱化佃tk:鯛べるものを設
ける。そして単位時間毎4=@告されたカウンタの値が
予め設置した数と比較してχさな埴であるとさ、簀麹な
発する構成とするとき、その間にJ!4富のあったこと
を離れt所で遺蓚に判断でさる。
Input/output control am setting roe, watchdog timer WD te,
A counter CWT and its 1sfiAIPyt are provided, and a sensor 118 is connected thereto. Counter ('NT has clock input terminal c'L's t'Ws fA one terminal Voo
, preset enable terminal 7B! , a counter output terminal 0) is provided, and this counter 0) may not be counted depending on the software on which the central processing unit IILcp'ry of the slave station is running. It is set to 11# which cannot be inserted. And program violence 11IL
This is to prevent #P from incurring 111 V 4 of the counter. The power source 1 of the Naori Unde ON is a backup type such as a storage battery, etc. Even in the event of a power outage of the Natori 1wM power source, the amount of the counter OMT is maintained. Then, the count is set to V), and it is done only when the operating power supply is turned on and when the backup power supply cannot be sustained due to a long-term power outage, and when the power supply is turned off. Therefore, when the watchdog timer WD detects an abnormal operation of the program using the conventional method and raises an interrupt to the central processing unit *cptr, the counter 01 counts the signal as a clock. Therefore, when the central control unit @00 of the master station M8 issues a command, the number of times the program abnormal operation occurs is determined by using the counter CNT of the slave station me as the main part of the communication device in each station. Further, as a device installed in the Chuten control device 00 of CHIN-guy B, unit #F
Kaya Tsukuda tk of the counter Ow〒: Set up something that can be eaten. Then, if the value of the counter notified by 4=@ is smaller than the preset number per unit time, and when the configuration is set to emit a large amount of air, during that time J! 4 I left the place where I was rich and decided to leave it behind.

m発明の効果 この五うC:して本発明によると比較旧簡易な装置で中
央処理装置におけるプログラムの異常動作が発生し、自
動伽旧をしたことについてその@数v婆嘉にチェックす
ることがでさるから、偶発的なものが、プログラムに弁
り欠陥が残っていたかを容ネー二判別でき遠方監初する
こと(;有効である。
Effects of the Invention 5C: According to the present invention, when an abnormal operation of a program in the central processing unit occurs in a simple device compared to the old one, it is possible to check the automatic obsolescence. Therefore, it is effective to perform remote monitoring to determine if there are any accidental defects in the program.

【図面の簡単な説明】 第1図は従来のウォッチドッグの構成Y示て内、 s2図はウォッチドッグタイ−r (:Lり中央処m装
置がツ噸ットされるia台の流れ[Y示す図、sS図は
本発明の一実施例1示すブロッグ惰l!図である。 OPυ−中央処理装置   丁勧・・・タイマνS 6
6局  SS・・・子局  νシ・・・メモリMOD連
讐・・−堂醤調器 X0C−・・入出力側1iniut YD〒・・・ウォッチドッグタイマ 01丁・・・カウンタ 0テ0・・・カウンタ個出力端子 特許出廟人 冨士通株式会社 代 理 人 紳土鈴木栄祐 手続補正書(自発) 1.事件の表示 昭和56年 特許 1第215125号2、発明の名称
  中央処理装置の真青復旧検出装置3、 補正をする
者 事件との関係  特許出願人 代表肴山本 卓眞 4、代理人 8、補正の内容 明細書の浄惜(内容(;汲史なし)手
続補正書(自発) 鈍な1 昭和1年2月【へUゝ 特許庁長冨 島田春樹 殿 1、事件の表示 昭和56 年 特許 願第2151251:2、発明の
名称  中央処理装置の異”i 空旧柳出装首3、 補
正をする者 事件との関係   %相出願人 工 ゎ(4祢) 522  菖士通株式費社代表省 山
 本 車 眞 4、代理人 6、補正により増加する発明の数  な し7、補正の
対象 発明の!1f−aな説明の掴 1面の(資)率な説明の徊 8、補正の内容 +1+  明細11I第3頁第8行「石ことが、」以後
塾9打F判断でF rxい。」までな[ることか、偶発
的Cユ起ったためで特に原因がないことか判断できない
。Jと補正する。 12:  明細書1JS6頁第9行「偶発的なものが、
」を「偶発チ1なものか、」と補正する。 +31  明細長第6頁弗13行Fウォッチドッグ」を
[ウオッチドヅグタイi」と補正する。
[Brief Description of the Drawings] Figure 1 shows the configuration of a conventional watchdog, and Figure s2 shows the flow of the watchdog tie-r (:L) where the central processing unit is connected. The diagrams shown in Y and sS are blog diagrams showing Embodiment 1 of the present invention.
6th station SS...Slave station ν...Memory MOD connection...-Douji adjuster ...Counter individual output terminal patent author Fujitsu Co., Ltd. Agent Eisuke Shindo Suzuki procedural amendment (voluntary) 1. Indication of the case 1982 Patent No. 1 No. 215125 2, Title of the invention True blue recovery detection device for central processing unit 3, Person making the amendment Relationship to the case Patent applicant representative Takuma Yamamoto 4, attorney 8, amendment Contents of the specification (Contents (no history)) Procedural amendment (spontaneous) Dull 1 February 1930 [To Uゝ Patent Office Director Tomi Haruki Shimada 1, Indication of the case 1982 Patent application no. 2151251:2, Title of the invention: Dissimilarity in the central processing unit 3, Relationship with the case of the person making the amendment % phase application artificial ゎ (4 熢) 522 Isushitsu Stock Exchange Representative Ministry Yamamoto Kurama 4, Agent 6, Number of inventions increased by amendment None 7, Grasping of a reasonable explanation of the invention subject to amendment 8, Contents of amendment + 1 + details 11I, page 3, line 8, ``Ishikoto...'' After that, it was determined that the cram school had a 9th stroke of F.'' It is not possible to determine whether this is due to an accidental C-yu occurrence and there is no particular cause.J 12: Specification 1JS page 6, line 9 “The accidental
” is corrected to ``Is it just a coincidence?'' +31 ``Watchdog'' on page 6, line 13 of the specification length is corrected to ``Watchdog I''.

Claims (1)

【特許請求の範囲】 1 中央外311装置からのアクセスによりセットされ
るタイマY設け、所定時間以内にリセットされないとき
中央外3!装置に対し割込みを上げるウォッチドッグタ
イマと、#ウォッチドッグタイマが割込みなよげた回1
19?計数するカウンタと、fiカウンタの餉を上位装
置へ連絡する通信装置とを具備することを特許とする中
央処理装置の異常復旧検出装置。 2 カウンタの個を受信する上位装置において単位時間
当りのカウンダ慣の変化な求め、それが所定像を超えた
と!、IF報を発することな特命とする特許請求の範囲
第1項記載の中央処理装置の異常り旧検出装置。
[Claims] 1. A timer Y is provided which is set by access from the outside central 311 device, and when it is not reset within a predetermined time, the outside central 3! A watchdog timer that raises an interrupt to the device and #1 when the watchdog timer interrupts an interrupt.
19? An abnormality recovery detection device for a central processing unit, which is patented as having a counter for counting and a communication device for communicating the value of the fi counter to a host device. 2. In the host device that receives the counter data, determine the change in the counter value per unit time, and if it exceeds the predetermined value! , an abnormality detection device for a central processing unit according to claim 1, which is specially ordered to issue an IF report.
JP56215125A 1981-12-31 1981-12-31 Fault recovery detector for central processing unit Pending JPS58119060A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56215125A JPS58119060A (en) 1981-12-31 1981-12-31 Fault recovery detector for central processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56215125A JPS58119060A (en) 1981-12-31 1981-12-31 Fault recovery detector for central processing unit

Publications (1)

Publication Number Publication Date
JPS58119060A true JPS58119060A (en) 1983-07-15

Family

ID=16667138

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56215125A Pending JPS58119060A (en) 1981-12-31 1981-12-31 Fault recovery detector for central processing unit

Country Status (1)

Country Link
JP (1) JPS58119060A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528005A (en) * 1991-07-19 1993-02-05 Nec Corp Malfunction detecting method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528005A (en) * 1991-07-19 1993-02-05 Nec Corp Malfunction detecting method
US5398332A (en) * 1991-07-19 1995-03-14 Nec Corporation System for detecting the malfunction of a CPU including a watchdog timer circuit and a memory for storing a malfunction count
JP2758742B2 (en) * 1991-07-19 1998-05-28 日本電気株式会社 Malfunction detection method

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