JPS58115502A - Multiple controller - Google Patents
Multiple controllerInfo
- Publication number
- JPS58115502A JPS58115502A JP21241881A JP21241881A JPS58115502A JP S58115502 A JPS58115502 A JP S58115502A JP 21241881 A JP21241881 A JP 21241881A JP 21241881 A JP21241881 A JP 21241881A JP S58115502 A JPS58115502 A JP S58115502A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- circuits
- outputs
- output
- controlling circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
- G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Safety Devices In Control Systems (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は、複数制御回路の出力のうち最適結果をみな
がら、常に他出力の補正を繰シ返すという多重化制御系
に関するものであ墨。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiplex control system that constantly repeats correction of other outputs while checking the optimum result among the outputs of a plurality of control circuits.
従来この種の装置として第1図に示すものがあった。図
は制御回路・を8重化したフィードバック制御系で(1
)は目標値設定器、(2) Fi図示の極性に加算する
加算器、(”) 、(8b)、(ac)は制御回路であ
シ同−仕様のものを8台使用している。(4)は入力信
号のうち最適信号を選出する選択回路、(6)は制御対
象である。また、第2図は選択回路(4)の内部構成を
示し、(4a+) 、 (4a2) 、 (4as)
(41)1) 、(4Th) 、 (4b+) 、 (
4ct) 。A conventional device of this type is shown in FIG. The figure shows a feedback control system with eight control circuits (1
) is a target value setter, (2) an adder that adds to the polarity shown in Fi, and (''), (8b), and (ac) are control circuits, and eight units of the same specification are used. (4) is a selection circuit that selects the optimal signal from among the input signals, and (6) is a control target.Furthermore, FIG. 2 shows the internal configuration of the selection circuit (4), and (4a+), (4a2), (4as)
(41)1) , (4Th) , (4b+) , (
4ct).
(402) −(4cs)はすべてダイオSド又は相当
品である。(402) - (4cs) are all diodes or equivalents.
次に動作について説明する。目標値設定器(1)で設定
された目標値とフィードバックされてくる制御蓋との偏
差を加算器(2)でとシ、制御回路(8a)。Next, the operation will be explained. The adder (2) calculates the deviation between the target value set by the target value setter (1) and the control lid fed back, and the control circuit (8a).
(8b)、(8c)に入力する。一般に、制御回路のゲ
インは、定常偏差を減少させるため大きな値に設定され
ている。制御回路(8a)、(8b)、(8c)は各々
独立に操作負の演算を行ない、選択回路(4)にょシ最
大、最小を除去中間の値を出方している制御回路の挫作
量を選出する。選択回路(4)は第2図で示されるよう
に、逆方向ダイオード(4at) 、 (4az)の並
列回路によ多制御回路(8a)、(8b)の出方の内部
さい方を選択する。同様にダイオード(4b+) −(
41’j)及び(4CIL(4at>により制御回路(
8b)と(8c)、 (8c)と(8a)の出力の内部
さい方を選択する。更に、選択された冬季さい出力の内
、順方向ダイオード(4ax)、(4b)。Input in (8b) and (8c). Generally, the gain of the control circuit is set to a large value in order to reduce steady-state deviation. The control circuits (8a), (8b), and (8c) each operate independently and perform negative calculations, and the selection circuit (4) removes the maximum and minimum values and outputs an intermediate value. Select quantity. As shown in Fig. 2, the selection circuit (4) selects the inner side of the output of the multi-control circuits (8a) and (8b) through the parallel circuit of reverse direction diodes (4at) and (4az). . Similarly, diode (4b+) −(
41'j) and (4CIL(4at>), the control circuit (
Select the internal size of the outputs of 8b) and (8c), (8c) and (8a). Furthermore, among the selected winter outputs, forward diodes (4ax), (4b).
(4cs)により最大値を選択することにより各制御回
路の8出力の内、中間の値を持つものを選択している。By selecting the maximum value using (4cs), the one having the intermediate value is selected from among the eight outputs of each control circuit.
次に選択回路(4)の出力は制御対象(6)に加えられ
る。このようにして制御回路を8重化したフィードバッ
ク制御系が実現されている。Next, the output of the selection circuit (4) is applied to the controlled object (6). In this way, a feedback control system with eight control circuits is realized.
従来の多重化制御装置は以上のように構成されているの
で、制御回路のゲインが大きいため湯度応答は不安定と
なりやすく、選択回路で選択されなかった制御回路の出
力は発散、飽和の恐れがあり、選択された制御回路との
出力誤差が大きいと、メンテナンス□等で制御回路の切
換え時に、不連続が発生し、安定始動までに時間がかか
るという欠点があった。Conventional multiplex control devices are configured as described above, so the hot water temperature response tends to be unstable due to the large gain of the control circuit, and the output of the control circuits not selected by the selection circuit is at risk of divergence and saturation. If there is a large output error with the selected control circuit, discontinuity will occur when switching the control circuit during maintenance, etc., and it will take time to reach a stable start.
この発明は上記のような従来のものの欠点を除去するた
めになされたもので、選択回路の出力と各制御回路の出
力の差に応じて、各制御回路の出力が一定の範囲内に収
まるよ゛、うに補正することにより、制御回路の連続切
換が”できる多重化制御装置を提供することを目的とし
ている。This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is designed to keep the output of each control circuit within a certain range according to the difference between the output of the selection circuit and the output of each control circuit. It is an object of the present invention to provide a multiplex control device that can perform continuous switching of control circuits by making the following corrections.
以下、この発明の一実施例を図について説明する。An embodiment of the present invention will be described below with reference to the drawings.
第8(8)において、(6a)、(6b)、(6o)は
同一仕様のゲイン調整回路、第4図はゲイン調整回路の
内部構成を示す図で、(5at)は加算器、(6ξ)は
不感帯を有するリミッタ、(8ζ)はサーボ機構による
駆動要素、(5a2)t−i可変抵抗である。In Section 8 (8), (6a), (6b), and (6o) are gain adjustment circuits with the same specifications, and FIG. 4 is a diagram showing the internal configuration of the gain adjustment circuit, (5at) is an adder, (6ξ ) is a limiter having a dead zone, (8ζ) is a driving element by a servo mechanism, and (5a2) is a t-i variable resistor.
また、第5図は他の実施例を示す歯で、(7a)、(W
b)、(7c)は入力調整回路、(8a) 、 (8b
) 、 (8c )は加算器である。Further, FIG. 5 shows teeth showing other embodiments, (7a), (W
b), (7c) are input adjustment circuits, (8a), (8b
) and (8c) are adders.
次に第8図、第4図の装置の動作について説明する。制
御回路(8a)、(8b)、(8c)の出力が選択回路
(4)に入力され中間値をもつ制御回路が選択されるに
到る経過は従来装置と同様である。Next, the operation of the apparatus shown in FIGS. 8 and 4 will be explained. The process by which the outputs of the control circuits (8a), (8b), and (8c) are input to the selection circuit (4) and the control circuit having the intermediate value is selected is the same as in the conventional device.
選択回路(4)の出力は各制御回路にフィードバックさ
れ、各制御回路の出力と共にゲイン調節回路(6a)
、 (6b)、 (6c)入力される。ゲイン調節回路
及び制御回路の内部構成は第4図に示される通シで、選
択回路の出力と制御回路の出力の差が加′n器((6a
l)で演算されるdの差が不感帯を有するリミッタ(6
−)により所定値より小さい場合には制御回路のパラメ
ータ補正を行なわず、所定値より大きい場合にはサーボ
11m構による駆動要素(Sat)を介して可変抵抗(
8aりを操作することによシ制御回路のゲインを調整し
て各制御回路の出力を一定範囲内に収めることができる
。The output of the selection circuit (4) is fed back to each control circuit, and the output of each control circuit is fed back to the gain adjustment circuit (6a).
, (6b), (6c) are input. The internal configuration of the gain adjustment circuit and the control circuit is the same as shown in FIG. 4, and the difference between the output of the selection circuit and the output of the control circuit is
The difference in d calculated in step l) is a limiter (6
-), if it is smaller than a predetermined value, the parameter correction of the control circuit is not performed, and if it is larger than a predetermined value, the variable resistance (
By operating 8a, the gain of each control circuit can be adjusted to keep the output of each control circuit within a certain range.
なお、上記実施例では制御回路内のゲイン定数の調整と
いう補正手段を用いたが、回路内の他のパラメータ(時
定数、リミッタ幅等)を補正しても上記実施例と同様の
効果を奏するっ
また、上記実施例では制御回路の内部パラメータ補正の
場合について説明したが、ディジタμ処理回路等のよう
に各制御回路の演算型式が全く同様であり、入力部のA
/ D変換器の誤差が主な原因と考えられる場合には
、第6図に示すように、選択回路の出力と各制御回路の
出力の差に応じた補正値を入力調整回路(7a) 、(
7b)、(7c)にて演算し、加算器(8a)、(8b
)、(8c)を介して入力信号を補正し1、各制御回路
の出力を一定範囲内に収めるようにしてもよい。Note that although the above embodiment used a correction means of adjusting the gain constant in the control circuit, the same effect as in the above embodiment can be achieved even if other parameters in the circuit (time constant, limiter width, etc.) are corrected. Furthermore, in the above embodiment, the case of internal parameter correction of the control circuit was explained, but the calculation type of each control circuit is exactly the same, such as a digital μ processing circuit, and the A of the input section is
/ If the error of the D converter is considered to be the main cause, as shown in Fig. 6, a correction value corresponding to the difference between the output of the selection circuit and the output of each control circuit is input to the input adjustment circuit (7a), (
7b) and (7c), and the adders (8a) and (8b
), (8c) may be used to correct the input signal 1 to keep the output of each control circuit within a certain range.
さらに、この発明では制御回路を8重化したフィードバ
ック制御系を例として説明したが、4重化以上のシステ
ムについても同様で、また、フィードバック制御系以外
にも適用可能である。Furthermore, although the present invention has been described using as an example a feedback control system in which the control circuits are 8-fold, the same applies to systems with 4-fold or higher circuits, and is also applicable to systems other than feedback control systems.
なお、制御回路の故障等によシ一定時間以上、出力が設
定範囲外におる場合には、その回路をシステムから離脱
するようにすれば望ましいことはない。Note that if the output is outside the set range for a certain period of time due to a failure of the control circuit, it is not desirable to remove that circuit from the system.
以上のように、この発明によれば、各制御回路の出力を
選択回路の出力を用いて補正できるように構成したので
、各制御回路の出力を一定範囲内に収めることができ、
制御回路の連続切換えができるものが得られる効果があ
る。As described above, according to the present invention, since the output of each control circuit can be corrected using the output of the selection circuit, the output of each control circuit can be kept within a certain range.
This has the effect of providing a control circuit that can be switched continuously.
第1図は従来の多重化制御装置のブロック図、第2図は
選択回路の構成図、第8図はこの発明の一実施例を示す
多重化制御装置のブロック図、第4図はこの発明のゲイ
ン調節回路の構成図、第5図はこの発明の他の実施例を
示す多重化制御装置のブロック図である。図において(
1)は目標値設定器、(2)は加算器、(8a)、(8
b)、(8c)は制御回路、(4)は選択回路、(5)
は制御対象、(6a)、 (6b) (6o )はゲイ
ン調節回路、(Sat)は加算器、C6”t)はリミッ
タ、(8a1)は駆動要素、(δξ獄可変抵抗である。
なお、図中間−符号は同一、又は相当部分を示す。
代理人 葛野信−(ほか1名)FIG. 1 is a block diagram of a conventional multiplex control device, FIG. 2 is a block diagram of a selection circuit, FIG. 8 is a block diagram of a multiplex control device showing an embodiment of the present invention, and FIG. 4 is a block diagram of a conventional multiplex control device. FIG. 5 is a block diagram of a multiplexing control device showing another embodiment of the present invention. In the figure (
1) is a target value setter, (2) is an adder, (8a), (8
b), (8c) are control circuits, (4) are selection circuits, (5)
is the controlled object, (6a), (6b) (6o) is the gain adjustment circuit, (Sat) is the adder, C6''t) is the limiter, (8a1) is the driving element, and (δξ variable resistance). Middle figure - Codes indicate the same or corresponding parts. Agent Makoto Kuzuno - (1 other person)
Claims (1)
これらの制御回路の出力のうち最適なものを選択する選
択回路と、この選択回路が選択する出力と各制御回路の
出力の差に応じて各制御回路の出力範囲を制限する補正
回路を備えた多重化制御装置。a plurality of control circuits that generate signals to control a controlled object;
It is equipped with a selection circuit that selects the optimal one among the outputs of these control circuits, and a correction circuit that limits the output range of each control circuit according to the difference between the output selected by this selection circuit and the output of each control circuit. Multiplex control equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21241881A JPS58115502A (en) | 1981-12-29 | 1981-12-29 | Multiple controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21241881A JPS58115502A (en) | 1981-12-29 | 1981-12-29 | Multiple controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58115502A true JPS58115502A (en) | 1983-07-09 |
Family
ID=16622252
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21241881A Pending JPS58115502A (en) | 1981-12-29 | 1981-12-29 | Multiple controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58115502A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61187001A (en) * | 1985-02-07 | 1986-08-20 | ウエスチングハウス エレクトリック コ−ポレ−ション | Analog output circuit network |
JPH07129247A (en) * | 1993-10-28 | 1995-05-19 | Tech Res & Dev Inst Of Japan Def Agency | Controller for electric hydraulic servo valve |
WO1997006471A1 (en) * | 1995-08-08 | 1997-02-20 | Siemens Aktiengesellschaft | Regulating system with at least two regulators and process for minimising the dead time of a regulating system |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS538547A (en) * | 1976-07-12 | 1978-01-26 | Mitsubishi Electric Corp | Feedback control unit |
-
1981
- 1981-12-29 JP JP21241881A patent/JPS58115502A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS538547A (en) * | 1976-07-12 | 1978-01-26 | Mitsubishi Electric Corp | Feedback control unit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61187001A (en) * | 1985-02-07 | 1986-08-20 | ウエスチングハウス エレクトリック コ−ポレ−ション | Analog output circuit network |
JPH07129247A (en) * | 1993-10-28 | 1995-05-19 | Tech Res & Dev Inst Of Japan Def Agency | Controller for electric hydraulic servo valve |
WO1997006471A1 (en) * | 1995-08-08 | 1997-02-20 | Siemens Aktiengesellschaft | Regulating system with at least two regulators and process for minimising the dead time of a regulating system |
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