JPS58114444A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58114444A JPS58114444A JP56213989A JP21398981A JPS58114444A JP S58114444 A JPS58114444 A JP S58114444A JP 56213989 A JP56213989 A JP 56213989A JP 21398981 A JP21398981 A JP 21398981A JP S58114444 A JPS58114444 A JP S58114444A
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor device
- pads
- short circuit
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明はセラミックパッケージを有する半導体装置の改
良に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to improvements in semiconductor devices having ceramic packages.
（２） 技術の背景
半導体装置は通常第１図に示すように半導体チップをセ
ラミックパッケージ内に気密封止する構成となっている
。図においてｌａ、ｌｂ、ｌｃは半導体チップ、２ａ、
２ｂ、２６はベース部材２１とふた部材２２とが接着層
を介して気密に固着されたセラミックパッケージ、３は
一端がセラミックパッケージ２内に固着され、但端がセ
ラミックパッケージ外に引き出された複数個のリード片
（第１図（ａ）のみ図示、他は省略）、４は半導体チッ
プユのポンディングパッドとリード片３とを電気的に接
続するボンディングワイヤである。(2) Background of the Technology A semiconductor device usually has a structure in which a semiconductor chip is hermetically sealed within a ceramic package, as shown in FIG. In the figure, la, lb, and lc are semiconductor chips, 2a,
2b and 26 are ceramic packages in which a base member 21 and a lid member 22 are hermetically fixed via an adhesive layer, and 3 is a plurality of ceramic packages in which one end is fixed inside the ceramic package 2, but one end is pulled out from the ceramic package. (only the lead piece shown in FIG. 1(a) is shown, the others are omitted); 4 is a bonding wire that electrically connects the bonding pad of the semiconductor chip and the lead piece 3;
このような半導体装置は、半導体チップｌａ。Such a semiconductor device is a semiconductor chip la.
ｌｂ、ｌｃのサイズが異るとそれに適合する第１図（ａ
）（ｂ）（ｃ）に示すような各種形状のセラミックパッ
ケージ２ａ％２１）、ｚｃが用いられている。しかし最
近の半導体チップサイズの多様化に対処するためにセラ
ミックパッケージを改良し、半導体のチップサイズが異
っても搭載可能で高信頼性なセラミックパッケージの実
現が要望されている。Figure 1 (a
Ceramic packages 2a%21) and zc of various shapes as shown in )(b)(c) are used. However, in order to cope with the recent diversification of semiconductor chip sizes, there is a need to improve ceramic packages and realize highly reliable ceramic packages that can be mounted even when semiconductor chips of different sizes are mounted.
（３） 従来技術と問題点・
従来のセラミックパッケージ２ａ％２ｂ、２０では、チ
ップサイズの小さな半導体チップ１ａを大きなセラミッ
クパッケ、−ジ２ｃＪＩＣ搭載するとボンディングワイ
ヤ４の空間に張られる長さが長くな９．ワイヤ間の接触
やワイヤのたれ下シによるショート事故が発生し易くな
る欠点があった。(3) Conventional technology and problems - In conventional ceramic packages 2a, 2b, 20, when a semiconductor chip 1a with a small chip size is mounted in a large ceramic package, the length stretched in the bonding wire 4 space becomes long. 9. There is a drawback that short-circuit accidents are likely to occur due to contact between wires or sagging of wires.
（４）発明の目的
本発明は上記従来の欠点を解消し、標準化された一種類
のパッケージにより、多種類の半導体チップの搭載を可
能とすることを目的とする。(4) Purpose of the Invention It is an object of the present invention to eliminate the above-mentioned conventional drawbacks and to make it possible to mount many types of semiconductor chips using one type of standardized package.
（５）考案の構成
そしてこの目的は本発明によればパッケージ内凹部に配
置した半導体チップ上の複数の電極を前記パッケージ端
部の対応する導電部材のパッドにワイヤボンディングし
て成る半導体装置において。(5) Structure and object of the invention According to the present invention, there is provided a semiconductor device in which a plurality of electrodes on a semiconductor chip arranged in a recess in a package are wire-bonded to corresponding pads of a conductive member at the end of the package.
前記パッケージ内の凹部の大きさを最大搭載半導体チッ
プに適合する様に形成すると共に前記パッケージ端部の
パッドに石って列状に複数個の補助パッド金配設して成
ることｔ−特徴とする半導体装置を提供することによっ
て達成される。The size of the recess in the package is formed to match the maximum mounted semiconductor chip, and a plurality of auxiliary pad metals are arranged in a row on the pad at the end of the package. This is achieved by providing a semiconductor device that achieves this goal.
（６） 発明の実施例 以下本発明の実施例を図面によって詳述する。(6) Examples of the invention Embodiments of the present invention will be described in detail below with reference to the drawings.
第２図は本発明によるパッケージのペース部材２１と搭
載した半導体チップ１とを示す断面図であシ、第３図は
そのベース部材２１の上面図である０
第２図は最大テップサイズに適合する凹部２１１を有す
るパッケージのペース部材２１を示している。チップサ
イズが小さい場合を示す第２図（ａ）では、半導体チッ
プ二のポンディングパッドからリード片へのボンディン
グワイヤ４はベース部材２１の凹部罠配設されたワイヤ
ボンディング補助パッド６を最短距離１結びながら配線
されている。補助パッド６を使用−ｆるため空間に張ら
れる１本当ｐのワイヤの長さを短くすることができワイ
ヤ間やワイヤのたれ下りによるショート事故を無くする
ことが可能となる。FIG. 2 is a cross-sectional view showing the space member 21 of the package according to the present invention and the mounted semiconductor chip 1, and FIG. 3 is a top view of the base member 21. FIG. 2 is adapted to the maximum tip size. 2 shows the pace member 21 of the package with a recess 211 that has a recess 211 therein. In FIG. 2(a), which shows the case where the chip size is small, the bonding wire 4 from the bonding pad of the semiconductor chip 2 to the lead piece is connected to the wire bonding auxiliary pad 6 disposed in the concave trap of the base member 21 by the shortest distance 1. Wired while tying. Since the auxiliary pad 6 is used, the length of one wire p stretched in the space can be shortened, and it is possible to eliminate short-circuit accidents caused by wires between wires or by sagging wires.
第３図に示した妄施例はワイヤボンディング補助ハツト
６ｔ−各辺に２列配設したものである。In the hypothetical embodiment shown in FIG. 3, two rows of wire bonding auxiliary hats 6t are arranged on each side.
図において３１はパッケージに固着されたＩＪ−ド片の
ポンディングパッドであシ、５拡牛導体チッフユをパッ
ケージに固着するダイアタッチ部を示している。各辺に
２列配設した補助パッド６はリード片のポンディングパ
ッド３１の数と同数であるが、これに制限されるもので
はない。また第２図（１））のような半導体チップ１の
場合には補助パすることが可能である。In the figure, reference numeral 31 indicates a bonding pad of an IJ-card piece fixed to the package, and indicates a die attach portion for fixing the expanded conductor chip to the package. The number of auxiliary pads 6 arranged in two rows on each side is the same as the number of bonding pads 31 on the lead piece, but the number is not limited to this. Further, in the case of the semiconductor chip 1 as shown in FIG. 2(1)), it is possible to provide an auxiliary pass.
なお本発明はパッケージの実装方法、例えばＤ工Ｐ（Ｄ
ｕａｌ ｉｎ ｐａｃｋａｇｅ ）、Ｆ Ｐ （Ｆ：Ｌ
ａｔ ｐａｃｋａｇｅ ）、Ｐ Ａ Ｐ （Ｐｉｎ ａ
ｒｒａｙ ｐａｃｋａｇｅ ）、１００（Ｌｅａｄｌｅ
ｓｓ ｃｈｉｐ ｃａｒｒｉｅｒ ）などの方法のいづ
れにも適用可能である。Note that the present invention relates to a package mounting method, for example, a D-process P (D
ual in package), F P (F:L
at package), P A P (Pin a
rray package), 100 (Leadle
It is applicable to any of the methods such as ss chip carrier).
（））発明の効果
本発明により従来１種類のパッケージにより搭載可能な
半導体チップサイズの許容幅は最大約２Ｕ程度であった
が、これｔ３倍以上に拡大することができパッケージ種
類の標準化による統一が可能となシ、またショート事故
が無くなるため高い信頼性が得られる効果を有する。()) Effects of the Invention With the present invention, the allowable width of the semiconductor chip size that can be mounted in one type of package was conventionally about 2U at maximum, but this can be expanded to more than 3 times, and it is possible to unify the size by standardizing the package types. This has the effect of increasing reliability by eliminating short-circuit accidents.
第３図は本発明によるパッケージペース部の上面図を示
している。
図において、１、ｌａ、ｌｂ、ｌｃは半導体チップ、２
．２ａ％ ２ｂ、２（！はパッケージ、２１はパッケー
ジベース部材、２２は）（ツケージふた部材、２１１は
パッケージ凹部、３はリード片、３１はリード片の・ポ
ンディングパッド、４はボンディングワイヤ、５はダイ
アタッチ部、６，６１．６２は補助パッドを示している
。FIG. 3 shows a top view of the package spacer according to the invention. In the figure, 1, la, lb, lc are semiconductor chips, 2
．． 2a% 2b, 2 (! is the package, 21 is the package base member, 22 is) (the cage lid member, 211 is the package recess, 3 is the lead piece, 31 is the lead piece / bonding pad, 4 is the bonding wire, 5 indicates a die attach portion, and 6, 61, and 62 indicate auxiliary pads.
Claims (1)
極を前記パッケージ端部の対応する導電部材のパッドに
ワイヤボンディングして成る半導体装置において、前記
パッケージ内の凹部の大きさを最大搭載半導体チップに
適合する様に形成すると共に前記パッケージ端部のパッ
ドに沿って列状に複数個の補助パッドを配設して成るこ
とｔ−特徴とする半導体装置っIn a semiconductor device in which a plurality of electrodes on dead and dead conductive chips are arranged in a recess in a package and are wire-bonded to corresponding pads of a conductive member at an end of the package, the size of the recess in the package is adjusted to the maximum mounted semiconductor chip. A semiconductor device characterized in that the semiconductor device is formed to fit the package and a plurality of auxiliary pads are arranged in a row along the pad at the end of the package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56213989A JPS58114444A (en) | 1981-12-26 | 1981-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56213989A JPS58114444A (en) | 1981-12-26 | 1981-12-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58114444A true JPS58114444A (en) | 1983-07-07 |
| JPS649734B2 JPS649734B2 (en) | 1989-02-20 |
Family
ID=16648405
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56213989A Granted JPS58114444A (en) | 1981-12-26 | 1981-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114444A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02196448A (en) * | 1989-01-25 | 1990-08-03 | Nec Corp | Semiconductor device |
| US5504373A (en) * | 1993-05-14 | 1996-04-02 | Samsung Electronics Co., Ltd. | Semiconductor memory module |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108369A (en) * | 1977-03-04 | 1978-09-21 | Hitachi Ltd | Electronic components |
-
1981
- 1981-12-26 JP JP56213989A patent/JPS58114444A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53108369A (en) * | 1977-03-04 | 1978-09-21 | Hitachi Ltd | Electronic components |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02196448A (en) * | 1989-01-25 | 1990-08-03 | Nec Corp | Semiconductor device |
| US5504373A (en) * | 1993-05-14 | 1996-04-02 | Samsung Electronics Co., Ltd. | Semiconductor memory module |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS649734B2 (en) | 1989-02-20 |
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