JPS58106976A - Time base corrector - Google Patents

Abstract

PURPOSE:To simplify the constitution and reduce the scale of the constitution in respect to the time base corrector for recording and reproducing of multitracks, by performing the control of line address commonly for all tracks. CONSTITUTION:Luminance signals Y1 and Y2 divided and recorded on tracks are reproduced and are supplied to input terminals 1A and 1B, and a red color signal R and a blue color signal B are supplied to input terminals 1C and 1D. These reproduced signals are supplied to write clock generating circuits 2A-2D to generate light clocks, and memories 4A-4D are operated by them. One of reproduced signals, for example, the red color signal R is supplied to a synchronizing signal separating circuit 5, and a reproduced synchronizing signal PBH separated by this circuit is supplied to a write address generating circuit 6. A write line address is generated by this circuit 6, and this line address is used commonly for memories 4A-4D.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a V'I'H time pace corrector that can simultaneously reproduce multi-channel video signals.

For example, when recording and reproducing a high-definition video signal with about twice the normal number of lines on a VTR, or when using a device with a slow relative speed between the rotating head and magnetic tape, the video signal is recorded line by line. It has been proposed to divide the data into multiple channels and to expand the time axis line by line and record them as separate tracks. When performing such multi-track recording and reproduction, it is necessary to provide a time pace corrector for each track to remove time axis fluctuations and compress the time axis of the reproduced signal.

In the past, the time pace collector for each track was operated completely independently, and there was a problem in that the configuration of the time pace corrector in multi-track recording and playback was complicated and large-scale.

The object of the present invention is to provide a time pace corrector in which such problems are solved, and the line address is commonly controlled for all tracks.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In FIG. A demodulated video signal is provided. A luminance signal Y1゜Y (including a burst signal and a synchronization signal) which has been divided into p tracks and recorded with time axis expansion is reproduced and supplied to the input terminals 1c and 1B, respectively. and in 1D,
A red signal R and a blue signal B (to which a burst signal and a synchronization signal are also added) are supplied. These reproduced signals are sent to the write clock generation circuit 2*t2B,
2cs2DVc is supplied, and a write clock and a write timing signal having an integer multiple of the color subcarrier frequency are formed from the burst signals contained in each.
/D converter 3*t3Bt3c+3n and memory 4
Am 4 B t 4 c * 4 p is operated.

Further, one of the above-mentioned reproduction signals, for example, a red signal, is supplied to the synchronization separation circuit 5, and a reproduction horizontal synchronization signal PBH separated by this signal K is supplied to the write address generation circuit 6. For example, a 3-bit write line address is generated by the write address generation circuit 6, and this line address is commonly used for the memories 4A to 4D. In addition, the reproduced vertical synchronization signal PBV from the synchronization separation circuit 5
is supplied to the second T, and the synchronizing signal PBV causes the latch 7 to block the line address at that timing.

This latched line address is the first line address of each field, and the read address generation circuit 8
is supplied to On the read side, the read clock generation circuit 10A1 is activated based on the reference video signal supplied from the terminal 9.
10B110Ce1u1) is the read clock and r
A timing signal is generated and supplied to memories 4A to 4D. At the same time, the reference video signal is supplied to the synchronization separation circuit 11, where the horizontal synchronization signals REF, H and vertical synchronization signals RE)I', V are separated.
11iJF.

H is supplied to the address counter of the read address generation circuit 8 as its clock input.

Further, the vertical synchronization (RI!: F, V) is supplied as a low r pulse to the read address generation circuit 8, and the first line address of the field stored in the latch 7 is loaded. The output of is supplied as the line address of memories 4A to 4D, and its least significant bit is used as a read enable signal for memories 4A and 4B.

The luminance signals read out alternately from the memos IJ-4A and 4B are time-axis compressed and have the original time axis.

The data read from each of the memories 4A to 4D is applied to the dropout compensation circuit 12A.

12B112Ct12D. The dropout (not shown) also envelopes the output of the playback amplifier! The detection result is detected from the level of the detection output, and the detection result is written to the corresponding line address as a flag of lvtsu). Of the output data read out from the memories 4A to 4D, the data in the horizontal section determined to have dropped out is compensated by being replaced with the average value of the correct data in the preceding and succeeding horizontal sections. The outputs of the dropout compensation circuits 12A and 12B are D/
It is supplied to the A converter 13A, and the output terminal 14A is
A luminance signal Y is obtained. Further, each output of the dropout compensation circuits 12C and 12D is connected to the D/A converter 13.
B and 13C, and a red signal R and a blue signal B are obtained at output terminals 14B and 14C, respectively.

An embodiment of the present invention having the above-described configuration will be described in further detail with reference to FIG. FIG. 2A shows the reference video signal supplied from terminal 9, FIG. 2B and FIG.
The reproduced brightness signal supplied to BK is shown, and the same figure is terminal 1C.
The red signal R (the same goes for the blue signal B) is shown. The number attached to each video signal indicates the line number within the / field. Based on the horizontal synchronizing signal PBHK separated from the red signal R, a pulse signal with a horizontal scanning frequency as shown in Fig. A line address is formed. Therefore, the line address numbers range from 0 to 7 as shown in Figure 1.
The number will change repeatedly until the number is reached.

For example, the line number of each channel of data written to line address number 0 of memories 4A to 4D, (
Yl-/θ'*"s-/02, R-103,
B-103). The 10th bit of the line address is the least significant bit of the R and B data address, and the 2nd
The 1 bit becomes the least significant bit of the address of the data Yl@Yz, and the line addresses of the memories 4A and 4B change at a period twice that shown in FIG. 2G.

In addition, in this embodiment, the rising and falling edges of the l bit are always offset by kOJH (H: horizontal interval) with respect to data R9BK, and by 0.2 with respect to data Y1,1.
! ; Specified to be in the H offset state.

In addition, from the Lee r address generation circuit 8,
Memo to show! A line address for 4A and 4El and a line address for memories 40 and 4D shown in the same drawing are generated, and furthermore, the l bit of this line address is made into the -Doinedel signal shown in FIG. and 4B. In the block diagram of FIG. 1, for simplicity, memories 4A and 4B and memory 40 are
and 4D, but in reality, as shown in Figure A and Figure A, there is an offset of 2H between them, and in the end, , the line numbers read out for the luminance signal and color signal are the same. Figure 1 K and line address (Figure 1 H) and line address signal (Figure 1 H)
Figure J) shows the luminance signal read out by K. The read clock of the luminance signal has a side wave number that is one times that of the write clock, so that the read clock has a time axis compressed. Also, from memories 40 and 4D, MK
As shown, a red signal R and a blue signal B are read out. And dropout compensation circuit 12A-73! Since there is a delay of /H due to D, reproduced data finally obtained is obtained having the same time relationship as the 1 reference video signal, as shown in FIG. 2N. The read clock is the reference ♂ Deo signal RR.
F, VID, and the output terminal 14
The luminance signal and chrominance signal obtained at A t 14 B+140 are those from which time axis fluctuations have been removed.

1. As mentioned above, control of 1 driver address is carried out in memories 4A to 4.
Since this is commonly performed for DK, the phase of the reproduced signal must not be shifted between tracks. In the case of self-recording and playback, there is almost no phase variation between tracks, but when other VT
At the time of compatible playback for playing back data recorded in R, the phase shift becomes large due to variations in the mounting positions of the plurality of heads between machines. This phase shift is 0. ! ; If there is a channel that exceeds H, that channel will produce a shift of /H in its output, resulting in color shift. Therefore, even during compatible playback, the phase difference between the playback signals from each shell is 0. ! ; Must be H or less.

In addition, when generating a line address based on the pulse formed from the reproduced horizontal synchronizing signal shown in Figure E, the lowest bit (2') is the same as that shown in Figure F.
If it becomes polar, the line number of each channel of the data to be written is (Yl-10/, Y, -1).
02, R-102D B-702), and the line numbers between the luminance signal and the chrominance signal are shifted by /H. Therefore, the result is obtained by controlling the read line address with an offset of 2H as described above. Looking at the data, the line number of the chrominance signal is advanced by /H with respect to the luminance signal, making them friends. Even in this case, if the read line address is set as an offset of /H, the line numbers of the luminance signal and color signal can be made the same. Therefore, in the write address generation circuit 6, for example, the luminance signal Y1.
It is set to 1 so that the lowest Vtco O of the line address is always 101 at the timing of the horizontal synchronization signal Y. Accordingly, it is possible to prevent the line numbers of the luminance signal and the color signal from being shifted in the output.

As can be understood from the description of the above-mentioned embodiment, according to the present invention, when the time axis fluctuation of the female video signal reproduced from a plurality of tracks is removed by the memory, the two-in-array of the memory is Control can be performed commonly for each track, and the circuit configuration can be simplified compared to the conventional arrangement in which an address control circuit is provided for each reproduction signal of each track.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 6A is a time chart used to explain the operation of an embodiment of the present invention. 1A to 1D...... Input terminal for playback signal, 4A to 4D... Memory, 6
・・・－・・・－・・・Write address generation circuit, 8
・・・・・・・・・Read address generation circuit. Agent Masato Sugiura

Claims (1)

[Claims] In a time pace corrector that reproduces a video signal recorded by dividing it into a plurality of tracks, and is equipped with a plurality of memories corresponding to the reproduced video signal, a time pace corrector is configured to reproduce a video signal that has been divided and recorded into a plurality of tracks, and a time pace collector that is provided with a plurality of memories corresponding to the reproduced video signal. The playback signal is written to the corresponding memory by a common line address formed on the basis of a synchronization signal separated from any of the playback video signals of the digital camera, and the 9-1 signal formed from the reference signal is written to the corresponding memory. 'A time pace corrector adapted to read out the playback video signal from the memory according to a clock and lead line address.