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JPS5798070A - Data processing device - Google Patents

Data processing device

Info

Publication number
JPS5798070A
JPS5798070A JP17543180A JP17543180A JPS5798070A JP S5798070 A JPS5798070 A JP S5798070A JP 17543180 A JP17543180 A JP 17543180A JP 17543180 A JP17543180 A JP 17543180A JP S5798070 A JPS5798070 A JP S5798070A
Authority
JP
Japan
Prior art keywords
register
main memory
section
write
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17543180A
Other languages
Japanese (ja)
Other versions
JPS6122830B2 (en
Inventor
Hiroshi Tamura
Shoji Nakatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17543180A priority Critical patent/JPS5798070A/en
Publication of JPS5798070A publication Critical patent/JPS5798070A/en
Publication of JPS6122830B2 publication Critical patent/JPS6122830B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To make the write-in and readout control to a main memory easy, by adjusting the timing of data transfer between a pipeline section and the main memory with a register, through the provision of a plurality of buffer registers corresponding to an access pipeline section. CONSTITUTION:An element read out from a main memory is transmitted to a data register 6, and inputted to a vector register section 1' having a plurality of vector registers with a plurality of interleaving via a buffer register 7. An output side of the register 7 is provided with a multiplexer 8 controlled with a buffer control circuit 9. An address, write-in and readout signal from a vector control circuit 10 controlled at the circuit 9 is added to each element of the register section 1'. The timing between the section 1' and the main memory is adjusted at the register 7 and the multiplexer 8 to make the write-in and readout control to the main memory area.
JP17543180A 1980-12-12 1980-12-12 Data processing device Granted JPS5798070A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17543180A JPS5798070A (en) 1980-12-12 1980-12-12 Data processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17543180A JPS5798070A (en) 1980-12-12 1980-12-12 Data processing device

Publications (2)

Publication Number Publication Date
JPS5798070A true JPS5798070A (en) 1982-06-18
JPS6122830B2 JPS6122830B2 (en) 1986-06-03

Family

ID=15995978

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17543180A Granted JPS5798070A (en) 1980-12-12 1980-12-12 Data processing device

Country Status (1)

Country Link
JP (1) JPS5798070A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043775A (en) * 1983-08-19 1985-03-08 Nec Corp Data processor
JPS6072069A (en) * 1983-09-28 1985-04-24 Nec Corp Vector operation processor
JPS60222969A (en) * 1984-04-20 1985-11-07 Fujitsu Ltd Pipeline controlling circuit
JPH0314073A (en) * 1989-06-13 1991-01-22 Koufu Nippon Denki Kk Vector processing system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH079293U (en) * 1993-07-14 1995-02-10 ナショナル住宅産業株式会社 Clothes rack

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837034A (en) * 1971-09-02 1973-05-31
JPS5491151A (en) * 1977-12-28 1979-07-19 Fujitsu Ltd Internal memory control system on array processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4837034A (en) * 1971-09-02 1973-05-31
JPS5491151A (en) * 1977-12-28 1979-07-19 Fujitsu Ltd Internal memory control system on array processor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6043775A (en) * 1983-08-19 1985-03-08 Nec Corp Data processor
JPH0332829B2 (en) * 1983-08-19 1991-05-14 Nippon Electric Co
JPS6072069A (en) * 1983-09-28 1985-04-24 Nec Corp Vector operation processor
JPS6248873B2 (en) * 1983-09-28 1987-10-15 Nippon Electric Co
JPS60222969A (en) * 1984-04-20 1985-11-07 Fujitsu Ltd Pipeline controlling circuit
JPH0321941B2 (en) * 1984-04-20 1991-03-25 Fujitsu Ltd
JPH0314073A (en) * 1989-06-13 1991-01-22 Koufu Nippon Denki Kk Vector processing system

Also Published As

Publication number Publication date
JPS6122830B2 (en) 1986-06-03

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