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JPS5791535A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5791535A
JPS5791535A JP16858280A JP16858280A JPS5791535A JP S5791535 A JPS5791535 A JP S5791535A JP 16858280 A JP16858280 A JP 16858280A JP 16858280 A JP16858280 A JP 16858280A JP S5791535 A JPS5791535 A JP S5791535A
Authority
JP
Japan
Prior art keywords
field
groove
insulating film
substrate
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16858280A
Other languages
Japanese (ja)
Other versions
JPS619737B2 (en
Inventor
Hiroshi Iwai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP16858280A priority Critical patent/JPS5791535A/en
Priority to US06/282,642 priority patent/US4394196A/en
Priority to DE8181105523T priority patent/DE3177018D1/en
Priority to EP86116670A priority patent/EP0245538B1/en
Priority to DE8686116670T priority patent/DE3177250D1/en
Priority to EP81105523A priority patent/EP0044082B1/en
Publication of JPS5791535A publication Critical patent/JPS5791535A/en
Publication of JPS619737B2 publication Critical patent/JPS619737B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To form a field insulating film having a large thickness in an arbitrary thickness without stepwise difference on the surface by etching the surface of a semiconductor substrate exposed between isolated insulating films and then oxidizing the field. CONSTITUTION:A narrow groove having a vertical side wall is formed with a mask of a resist film, a channel stopper region 34 is formed by the injection of boron, an insulating film is accumulated, and the groove is then buried. Thereafter, a silicon substrate 31 is exposed until the surface of the substrate 31 is exposed, and burying field insulating films 361-363 remain. Thereafter, an oxidation resistant film 38 is patterned with the resist film 39, the substrate 31 is etched, and a groove 40 is formed. Then, a P<+>-type region 41 is formed on the bottom of the groove, is oxidized in the field, and a field insulating film 42 having wide width is formed. Thus, the field insulating film having flat surface without bird beak can be formed.
JP16858280A 1980-07-16 1980-11-29 Manufacture of semiconductor device Granted JPS5791535A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP16858280A JPS5791535A (en) 1980-11-29 1980-11-29 Manufacture of semiconductor device
US06/282,642 US4394196A (en) 1980-07-16 1981-07-13 Method of etching, refilling and etching dielectric grooves for isolating micron size device regions
DE8181105523T DE3177018D1 (en) 1980-07-16 1981-07-14 Method of manufacturing a semiconductor device comprising a dielectric insulating region
EP86116670A EP0245538B1 (en) 1980-07-16 1981-07-14 Method for manufacturing a semiconductor device comprising dielectric isolation regions
DE8686116670T DE3177250D1 (en) 1980-07-16 1981-07-14 METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT WITH DIELECTRIC INSULATION ZONES.
EP81105523A EP0044082B1 (en) 1980-07-16 1981-07-14 Method of manufacturing a semiconductor device comprising a dielectric insulating region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16858280A JPS5791535A (en) 1980-11-29 1980-11-29 Manufacture of semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP62001804A Division JPS62162343A (en) 1987-01-09 1987-01-09 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5791535A true JPS5791535A (en) 1982-06-07
JPS619737B2 JPS619737B2 (en) 1986-03-25

Family

ID=15870721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16858280A Granted JPS5791535A (en) 1980-07-16 1980-11-29 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5791535A (en)

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121951A (en) * 1982-12-28 1984-07-14 Fujitsu Ltd Semiconductor device and its manufacturing method
JPS6045036A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Substrate structure of semiconductor device and manufacture thereof
JPS6045037A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Substrate structure of semiconductor device and manufacture thereof
US4980311A (en) * 1987-05-05 1990-12-25 Seiko Epson Corporation Method of fabricating a semiconductor device
US5371036A (en) * 1994-05-11 1994-12-06 United Microelectronics Corporation Locos technology with narrow silicon trench
US5895255A (en) * 1994-11-30 1999-04-20 Kabushiki Kaisha Toshiba Shallow trench isolation formation with deep trench cap
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5981357A (en) * 1996-04-10 1999-11-09 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology
US8420453B2 (en) 2009-08-18 2013-04-16 Samsung Electronics Co., Ltd. Method of forming active region structure

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108748A (en) * 1979-02-14 1980-08-21 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit device and manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108748A (en) * 1979-02-14 1980-08-21 Nippon Telegr & Teleph Corp <Ntt> Semiconductor integrated circuit device and manufacture thereof

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121951A (en) * 1982-12-28 1984-07-14 Fujitsu Ltd Semiconductor device and its manufacturing method
JPS6045036A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Substrate structure of semiconductor device and manufacture thereof
JPS6045037A (en) * 1983-08-23 1985-03-11 Nippon Telegr & Teleph Corp <Ntt> Substrate structure of semiconductor device and manufacture thereof
US4980311A (en) * 1987-05-05 1990-12-25 Seiko Epson Corporation Method of fabricating a semiconductor device
US5371036A (en) * 1994-05-11 1994-12-06 United Microelectronics Corporation Locos technology with narrow silicon trench
US5895255A (en) * 1994-11-30 1999-04-20 Kabushiki Kaisha Toshiba Shallow trench isolation formation with deep trench cap
US5904539A (en) * 1996-03-21 1999-05-18 Advanced Micro Devices, Inc. Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties
US5981357A (en) * 1996-04-10 1999-11-09 Advanced Micro Devices, Inc. Semiconductor trench isolation with improved planarization methodology
US5926713A (en) * 1996-04-17 1999-07-20 Advanced Micro Devices, Inc. Method for achieving global planarization by forming minimum mesas in large field areas
US5899727A (en) * 1996-05-02 1999-05-04 Advanced Micro Devices, Inc. Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US6353253B2 (en) 1996-05-02 2002-03-05 Advanced Micro Devices, Inc. Semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization
US8420453B2 (en) 2009-08-18 2013-04-16 Samsung Electronics Co., Ltd. Method of forming active region structure

Also Published As

Publication number Publication date
JPS619737B2 (en) 1986-03-25

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