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JPS5771579A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS5771579A
JPS5771579A JP55147771A JP14777180A JPS5771579A JP S5771579 A JPS5771579 A JP S5771579A JP 55147771 A JP55147771 A JP 55147771A JP 14777180 A JP14777180 A JP 14777180A JP S5771579 A JPS5771579 A JP S5771579A
Authority
JP
Japan
Prior art keywords
read
voltage
precharged
vss
vcc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55147771A
Other languages
Japanese (ja)
Inventor
Yoshihiro Takemae
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55147771A priority Critical patent/JPS5771579A/en
Priority to US06/313,616 priority patent/US4458336A/en
Priority to DE8181304967T priority patent/DE3176601D1/en
Priority to IE2483/81A priority patent/IE53512B1/en
Priority to EP87104318A priority patent/EP0239913B2/en
Priority to EP81304967A priority patent/EP0050529B1/en
Priority to DE8787104318T priority patent/DE3177221D1/en
Publication of JPS5771579A publication Critical patent/JPS5771579A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To make a dummy cell unnecessary and also to increase a read-out speed, by precharging a pair of bit lines of a memory device of a 1 transistor and 1 capacitor type, to the same potential which has been prescribed. CONSTITUTION:A pair of bit lines BL and an anti-BL are precharged to voltage (Vcc-Vss)/2 by making a bit line clock BC on a high level, turning on a transistor O3 balancing by discharge to a bit line to the low potential side, and also compensating the leak voltage by an electric power supplying circuit PS2 formed by resistances R3, R3. In this way, information is read out through the line BL and the anti- BL having an equal variation width, one of which is precharged to Vcc and the other to Vss, respectively, in accordance with memory contents of a cell MC by a sense amplifier SA amplifier SA and an active pull-up circuit APC1 or AFC2. According to this constitution, a dummy cell, etc. become unnecessary, also back gate voltage is stabilized, and read-out is executed at a high speed.
JP55147771A 1980-10-22 1980-10-22 Semiconductor memory device Pending JPS5771579A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP55147771A JPS5771579A (en) 1980-10-22 1980-10-22 Semiconductor memory device
US06/313,616 US4458336A (en) 1980-10-22 1981-10-21 Semiconductor memory circuit
DE8181304967T DE3176601D1 (en) 1980-10-22 1981-10-22 Semiconductor memory circuit
IE2483/81A IE53512B1 (en) 1980-10-22 1981-10-22 Semiconductor memory circuit
EP87104318A EP0239913B2 (en) 1980-10-22 1981-10-22 Semiconductor memory circuit
EP81304967A EP0050529B1 (en) 1980-10-22 1981-10-22 Semiconductor memory circuit
DE8787104318T DE3177221D1 (en) 1980-10-22 1981-10-22 SEMICONDUCTOR MEMORY CIRCUIT.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55147771A JPS5771579A (en) 1980-10-22 1980-10-22 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS5771579A true JPS5771579A (en) 1982-05-04

Family

ID=15437803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55147771A Pending JPS5771579A (en) 1980-10-22 1980-10-22 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS5771579A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60212894A (en) * 1984-04-06 1985-10-25 Hitachi Ltd Dynamic ram
JPS61158095A (en) * 1984-12-28 1986-07-17 Toshiba Corp Bit line precharge circuit of dynamic memory
US5446694A (en) * 1993-04-28 1995-08-29 Oki Electric Industry Co., Ltd. Semiconductor memory device
WO2002101747A3 (en) * 2001-06-11 2003-04-24 Analog Devices Inc Draw with bit line precharging, inverting data writing, retained data output and reduced power consumption
JP2010157919A (en) * 2008-12-26 2010-07-15 Fujitsu Semiconductor Ltd Semiconductor integrated circuit, data transfer system and method for transfer data
JP2011034614A (en) * 2009-07-30 2011-02-17 Elpida Memory Inc Semiconductor device, and system including the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52152129A (en) * 1976-06-14 1977-12-17 Nippon Telegr & Teleph Corp <Ntt> Memory signal detection-amplification unit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52152129A (en) * 1976-06-14 1977-12-17 Nippon Telegr & Teleph Corp <Ntt> Memory signal detection-amplification unit

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60212894A (en) * 1984-04-06 1985-10-25 Hitachi Ltd Dynamic ram
JPS61158095A (en) * 1984-12-28 1986-07-17 Toshiba Corp Bit line precharge circuit of dynamic memory
US5446694A (en) * 1993-04-28 1995-08-29 Oki Electric Industry Co., Ltd. Semiconductor memory device
WO2002101747A3 (en) * 2001-06-11 2003-04-24 Analog Devices Inc Draw with bit line precharging, inverting data writing, retained data output and reduced power consumption
CN100386818C (en) * 2001-06-11 2008-05-07 模拟装置公司 Low power hynamic RAM with bit line pre-charge, inversion data write and storing data output
JP2010157919A (en) * 2008-12-26 2010-07-15 Fujitsu Semiconductor Ltd Semiconductor integrated circuit, data transfer system and method for transfer data
JP2011034614A (en) * 2009-07-30 2011-02-17 Elpida Memory Inc Semiconductor device, and system including the same
US8665625B2 (en) 2009-07-30 2014-03-04 Elpida Memory, Inc. Semiconductor device having hierarchically structured bit lines and system including the same
US8773884B2 (en) 2009-07-30 2014-07-08 Seiji Narui Semiconductor device having hierarchically structured bit lines and system including the same

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