JPS5760752A - Data processing device - Google Patents
Data processing deviceInfo
- Publication number
- JPS5760752A JPS5760752A JP13472280A JP13472280A JPS5760752A JP S5760752 A JPS5760752 A JP S5760752A JP 13472280 A JP13472280 A JP 13472280A JP 13472280 A JP13472280 A JP 13472280A JP S5760752 A JPS5760752 A JP S5760752A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- error
- data
- parity
- checker
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
- G11B20/1806—Pulse code modulation systems for audio signals
- G11B20/1813—Pulse code modulation systems for audio signals by adding special bits or symbols to the coded information
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Error Detection And Correction (AREA)
Abstract
PURPOSE:To use redundant bits of a minimum to not only discriminate whether an error exists or not by an error flag but also cope with a soft error, by adding a parity bit to every word before data is written to an RAM. CONSTITUTION:Reproduced data is supplied to an input terminal 1 and is subjected to error detection by a CRC checker 2. In accordance with the error detection result of the checker 2, a flag bit Fi is generated by a flag bit generating circuit 5 and is applied to an exclusive OR gate 6. Reproduced data to which the parity bit is added by the checker 2 is delayed in a delay circuit 3 by a prescribed time, and a parity bit Pi is applied to the gate 6 from a parity generating circuit 4 at the timing synchronized with the bit Fi. The output bit, which indicates that an error exists, from the gate 6 and output data from the circuit 4 are written to an RAM7, and data and the parity bit read out from the RAM7 are checked by a parity checker 8, thus checking data as well as a soft error.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13472280A JPS5760752A (en) | 1980-09-27 | 1980-09-27 | Data processing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13472280A JPS5760752A (en) | 1980-09-27 | 1980-09-27 | Data processing device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5760752A true JPS5760752A (en) | 1982-04-12 |
Family
ID=15135063
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13472280A Pending JPS5760752A (en) | 1980-09-27 | 1980-09-27 | Data processing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5760752A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0794666A3 (en) * | 1988-08-05 | 1998-10-21 | Canon Kabushiki Kaisha | Information transmission system with record/reproducing device |
-
1980
- 1980-09-27 JP JP13472280A patent/JPS5760752A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0794666A3 (en) * | 1988-08-05 | 1998-10-21 | Canon Kabushiki Kaisha | Information transmission system with record/reproducing device |
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