JPS5755437A - Interrupting signal detector - Google Patents
Interrupting signal detectorInfo
- Publication number
- JPS5755437A JPS5755437A JP12921480A JP12921480A JPS5755437A JP S5755437 A JPS5755437 A JP S5755437A JP 12921480 A JP12921480 A JP 12921480A JP 12921480 A JP12921480 A JP 12921480A JP S5755437 A JPS5755437 A JP S5755437A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- interrupting
- interruption
- gate
- irq
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
- G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To prevent pseudo interruption due to noise, by allowing a central processing unit to receive the interruption, only when a timing signal coincides with an interruption signal produced for a constant period. CONSTITUTION:Signal lines l1, l2 and l3, l4 are coupled via a central processing unit CPU having functions to receive interruption signals and external devices I/O which produce the interruption signals through an interface buffer VIA which executes the interrupting function. The CPU and the VIA are connected via an AND gate G at interrupting signal lines IRQ, IRQ' via the AND gate G, and pulses with a specified period from a timing signal generating circuit TMG is inputted to other inputs of the gate G. The interrupting signal from the VIA is transmitted to an interrupting signal line IRQ, and the gate G transmits an output to the CPU, only when the signal coincides with the pulse from the TMG. Thus, the production of an artificial interrupting signal due to noise as shown by F, G in Figures is prevented to prevent a malfunction for the entire system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12921480A JPS5755437A (en) | 1980-09-19 | 1980-09-19 | Interrupting signal detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12921480A JPS5755437A (en) | 1980-09-19 | 1980-09-19 | Interrupting signal detector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5755437A true JPS5755437A (en) | 1982-04-02 |
Family
ID=15003950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12921480A Pending JPS5755437A (en) | 1980-09-19 | 1980-09-19 | Interrupting signal detector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5755437A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6228837A (en) * | 1985-07-31 | 1987-02-06 | Toshiba Corp | Interruption signal control system |
| JPS63142402A (en) * | 1986-12-04 | 1988-06-14 | Fujitsu Ten Ltd | Method for data reception from successive comparison type a/d converter |
-
1980
- 1980-09-19 JP JP12921480A patent/JPS5755437A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6228837A (en) * | 1985-07-31 | 1987-02-06 | Toshiba Corp | Interruption signal control system |
| JPS63142402A (en) * | 1986-12-04 | 1988-06-14 | Fujitsu Ten Ltd | Method for data reception from successive comparison type a/d converter |
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