JPS5745754A - Clock pickup circuit for dmi code train - Google Patents
Clock pickup circuit for dmi code trainInfo
- Publication number
- JPS5745754A JPS5745754A JP55120760A JP12076080A JPS5745754A JP S5745754 A JPS5745754 A JP S5745754A JP 55120760 A JP55120760 A JP 55120760A JP 12076080 A JP12076080 A JP 12076080A JP S5745754 A JPS5745754 A JP S5745754A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- code train
- output
- signal
- enor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To directly pick up a clock signal of a differentiation mark transposition code train with a simple constitution, by adding the differentiation mark transposition code train to a delay circuit, AND circuit and NOR circuit and outputting the sum via an FF, and logical circuit of exclusive logical NOR circuit. CONSTITUTION:A delay circuit DLY delays a differentiation mark transposition DMI code train (a) by T/2 (where: T=1/f0, and f0 is a clock frequency) to output a code train (b). The output (c) of an AND circuit for input code trains (a) and (b) corresponds to a binary non-zero return NRZ data 1 coded at 11, and the output (d) of an NOR circuit NOR in which the logic is at inversion (a+b) corresponds to 1 of the NRZ data coded to 00. The FF is set to leading of the signals (c), (d) and a signal (e) is applied to one terminal of an exclusive logical sum NOT circuit ENOR. A code train (b) is applied to another input terminal of the circuit ENOR and the signal (c) is applied to other input terminal, and an output (f) of the circuit ENOR is applied to an OR circuit OR with the signal (d) and a clock signal (g) in frequency f0 is outputted from the circuit OR.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55120760A JPS5745754A (en) | 1980-09-01 | 1980-09-01 | Clock pickup circuit for dmi code train |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55120760A JPS5745754A (en) | 1980-09-01 | 1980-09-01 | Clock pickup circuit for dmi code train |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5745754A true JPS5745754A (en) | 1982-03-15 |
Family
ID=14794308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55120760A Pending JPS5745754A (en) | 1980-09-01 | 1980-09-01 | Clock pickup circuit for dmi code train |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5745754A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4965264A (en) * | 1987-03-25 | 1990-10-23 | Yoshitomi Pharmaceutical Industries, Ltd. | Thienocinnoline compounds and their pharmaceutical use |
| US5760032A (en) * | 1994-06-01 | 1998-06-02 | Yoshitomi Pharmaceutical Industries, Ltd. | Thienylazole compound and thienotriazolodiazepine compound |
-
1980
- 1980-09-01 JP JP55120760A patent/JPS5745754A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4965264A (en) * | 1987-03-25 | 1990-10-23 | Yoshitomi Pharmaceutical Industries, Ltd. | Thienocinnoline compounds and their pharmaceutical use |
| US5760032A (en) * | 1994-06-01 | 1998-06-02 | Yoshitomi Pharmaceutical Industries, Ltd. | Thienylazole compound and thienotriazolodiazepine compound |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| GB1504449A (en) | Tion | |
| JPS56152373A (en) | Laser recording device | |
| ES8504582A1 (en) | Modulation system for railway circuits. | |
| DE3851001D1 (en) | Clock scheme for a VLSI system. | |
| EP0390037A3 (en) | Pitch shift apparatus | |
| KR890006010A (en) | FM radio receiver | |
| JPS5745754A (en) | Clock pickup circuit for dmi code train | |
| US4100541A (en) | High speed manchester encoder | |
| GB1212340A (en) | Transmission system comprising a transmitter and a receiver for the transmission of information in a prescribed frequency band | |
| DE60131164D1 (en) | Receiver with three decision circuits | |
| ATE51984T1 (en) | CIRCUIT FOR REGENERATION OF PERIODIC SIGNALS. | |
| DE3683668D1 (en) | CIRCUIT ARRANGEMENT FOR EARTH-FREE TRANSMISSION OF DIGITAL SIGNALS THROUGH DISCONNECTORS. | |
| US4806907A (en) | Apparatus and method for digital data transmission | |
| GB1412156A (en) | Pulse amplitude-modulated signal transmission systems | |
| DE3882114D1 (en) | METHOD FOR TRANSMITTING A DIGITAL SIGNAL. | |
| GB947430A (en) | Improvements in or relating to pulse-code modulation transmission systems | |
| JPS57112158A (en) | Code converting circuit | |
| JPS57136845A (en) | Coding and transfer system of information data | |
| ATE44330T1 (en) | METHOD OF RECORDING A PCM AUDIO SIGNAL WITH COMPENSATION OF SIGNAL INTERFERENCE. | |
| ES451439A1 (en) | Clock signal and auxiliary signal transmission system | |
| JPS57198593A (en) | Memory circuit | |
| JPS57106264A (en) | System for data reproducing | |
| JPS5710564A (en) | Digital signal converting circuit | |
| GB1155623A (en) | Error Reduction Coding for Digital Facsimile | |
| JPS609253A (en) | Signal transmitting method |