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JPS5739448A - Carrying circuit of binary adder - Google Patents

Carrying circuit of binary adder

Info

Publication number
JPS5739448A
JPS5739448A JP11360180A JP11360180A JPS5739448A JP S5739448 A JPS5739448 A JP S5739448A JP 11360180 A JP11360180 A JP 11360180A JP 11360180 A JP11360180 A JP 11360180A JP S5739448 A JPS5739448 A JP S5739448A
Authority
JP
Japan
Prior art keywords
logical
circuit
logical circuit
expression
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11360180A
Other languages
Japanese (ja)
Other versions
JPS6161409B2 (en
Inventor
Takashi Soma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RIKEN Institute of Physical and Chemical Research
Original Assignee
RIKEN Institute of Physical and Chemical Research
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RIKEN Institute of Physical and Chemical Research filed Critical RIKEN Institute of Physical and Chemical Research
Priority to JP11360180A priority Critical patent/JPS5739448A/en
Publication of JPS5739448A publication Critical patent/JPS5739448A/en
Publication of JPS6161409B2 publication Critical patent/JPS6161409B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To operate a carrying circuit in high speed as a whole, by balancing a logical complexity (logical depth) of a logical circuit GP for generating Gn, Pn, and a logical circuit C for generating Cn. CONSTITUTION:For instance, when an augend and an addend are made An and Bn, respectively, the sum Sn is derived by the expression Sn=An+Bn+Cn-1 shows carry to n-th digit). When executing this addition, the expression is deformed as Gn=AnBn, Pn=An+Bn, Cn=Cn+Cn-1.Pn, and it is derived by a logical circuit GP for generating Gn, Pn, a logical circuit C for deciding Cn and a logical circuit S for deciding Sn. Also, it is further deformed as the expression (6) and the expression (7), and a logical circuit based on them is prepared. According to this constitution, logical depths (logical complexties) of the logical circuit GP and the logical circuit C are balanced, and a carrying circuit is operated in a high speed as a whole.
JP11360180A 1980-08-19 1980-08-19 Carrying circuit of binary adder Granted JPS5739448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11360180A JPS5739448A (en) 1980-08-19 1980-08-19 Carrying circuit of binary adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11360180A JPS5739448A (en) 1980-08-19 1980-08-19 Carrying circuit of binary adder

Publications (2)

Publication Number Publication Date
JPS5739448A true JPS5739448A (en) 1982-03-04
JPS6161409B2 JPS6161409B2 (en) 1986-12-25

Family

ID=14616340

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11360180A Granted JPS5739448A (en) 1980-08-19 1980-08-19 Carrying circuit of binary adder

Country Status (1)

Country Link
JP (1) JPS5739448A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6143341A (en) * 1984-08-07 1986-03-01 Nec Corp Adder circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS521242A (en) * 1975-06-23 1977-01-07 Kenji Tajima Ignition plug of internal combustion engine
JPS5249119A (en) * 1975-10-10 1977-04-19 Florida Data Corp Styus type mechanism
JPS5315407A (en) * 1976-07-26 1978-02-13 Toho Iyaku Kenkyusho:Kk New preparation of cephalothin
JPS5410872A (en) * 1977-06-27 1979-01-26 Hokushin Electric Works Adjusting meter having output preset function

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS521242A (en) * 1975-06-23 1977-01-07 Kenji Tajima Ignition plug of internal combustion engine
JPS5249119A (en) * 1975-10-10 1977-04-19 Florida Data Corp Styus type mechanism
JPS5315407A (en) * 1976-07-26 1978-02-13 Toho Iyaku Kenkyusho:Kk New preparation of cephalothin
JPS5410872A (en) * 1977-06-27 1979-01-26 Hokushin Electric Works Adjusting meter having output preset function

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6143341A (en) * 1984-08-07 1986-03-01 Nec Corp Adder circuit
JPH0421889B2 (en) * 1984-08-07 1992-04-14 Nippon Electric Co

Also Published As

Publication number Publication date
JPS6161409B2 (en) 1986-12-25

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