JPS5734375A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS5734375A JPS5734375A JP10994380A JP10994380A JPS5734375A JP S5734375 A JPS5734375 A JP S5734375A JP 10994380 A JP10994380 A JP 10994380A JP 10994380 A JP10994380 A JP 10994380A JP S5734375 A JPS5734375 A JP S5734375A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- integrated circuit
- signal processing
- processing circuit
- element region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 238000006243 chemical reaction Methods 0.000 abstract 3
- 239000011347 resin Substances 0.000 abstract 2
- 229920005989 resin Polymers 0.000 abstract 2
- 238000000465 moulding Methods 0.000 abstract 1
- 238000012216 screening Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/1443—Devices controlled by radiation with at least one potential jump or surface barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Light Receiving Elements (AREA)
Abstract
PURPOSE:To obtain an integrated circuit of high reliability through avoiding incidence of light into a signal processing circuit element region by an arrangement in which a photoelectric conversion element region and a signal processing circuit element region are separated in an integrated circuit containing a photoelectric conversion element inside it and the signal processing circuit element region is fixed in the reverse direction. CONSTITUTION:A photoelectric conversion element chip 1 and a signal processing circuit element chip 2 are separated individually each other and an integrated circuit is built by molding them using transparent resin 5. In this arrangement the chip 1 is fixed on an upper end of a lead frame 3 which protrudes out the resin 5 pointed incident surface upward, and they are connected with a bonding wire 4. And the chip 2 is fixed on the chip 3 by face-down bonding. By this arrangement an incident light to the chip 1 can not get into the chip 2 and it is possible to fabricate an error- free integrated circuit without any special light screening part.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55109943A JPS6027196B2 (en) | 1980-08-08 | 1980-08-08 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55109943A JPS6027196B2 (en) | 1980-08-08 | 1980-08-08 | Semiconductor integrated circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5734375A true JPS5734375A (en) | 1982-02-24 |
JPS6027196B2 JPS6027196B2 (en) | 1985-06-27 |
Family
ID=14523039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55109943A Expired JPS6027196B2 (en) | 1980-08-08 | 1980-08-08 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6027196B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6132480A (en) * | 1984-07-24 | 1986-02-15 | Canon Inc | Photosensor |
JPH0444388U (en) * | 1990-08-10 | 1992-04-15 | ||
JPH05259483A (en) * | 1992-01-14 | 1993-10-08 | Samsung Electron Co Ltd | Semiconductor package for photoelectric conversion |
US5357121A (en) * | 1991-10-14 | 1994-10-18 | Mitsubishi Denki Kabushiki Kaisha | Optoelectronic integrated circuit |
CN113013288A (en) * | 2021-02-05 | 2021-06-22 | 广东省大湾区集成电路与系统应用研究院 | Integration structure and integration method of detector |
-
1980
- 1980-08-08 JP JP55109943A patent/JPS6027196B2/en not_active Expired
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6132480A (en) * | 1984-07-24 | 1986-02-15 | Canon Inc | Photosensor |
JPH0476221B2 (en) * | 1984-07-24 | 1992-12-03 | Canon Kk | |
JPH0444388U (en) * | 1990-08-10 | 1992-04-15 | ||
US5357121A (en) * | 1991-10-14 | 1994-10-18 | Mitsubishi Denki Kabushiki Kaisha | Optoelectronic integrated circuit |
JPH05259483A (en) * | 1992-01-14 | 1993-10-08 | Samsung Electron Co Ltd | Semiconductor package for photoelectric conversion |
CN113013288A (en) * | 2021-02-05 | 2021-06-22 | 广东省大湾区集成电路与系统应用研究院 | Integration structure and integration method of detector |
Also Published As
Publication number | Publication date |
---|---|
JPS6027196B2 (en) | 1985-06-27 |
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