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JPS5733476A - Buffer memory control system - Google Patents

Buffer memory control system

Info

Publication number
JPS5733476A
JPS5733476A JP10555180A JP10555180A JPS5733476A JP S5733476 A JPS5733476 A JP S5733476A JP 10555180 A JP10555180 A JP 10555180A JP 10555180 A JP10555180 A JP 10555180A JP S5733476 A JPS5733476 A JP S5733476A
Authority
JP
Japan
Prior art keywords
address
length
main memory
buffer memory
compared
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10555180A
Other languages
Japanese (ja)
Inventor
Matao Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10555180A priority Critical patent/JPS5733476A/en
Publication of JPS5733476A publication Critical patent/JPS5733476A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To realize a high-speed MOVE instruction that satisfies the specific conditions, by obtaining no coincidence of contents between a main memory and a buffer. CONSTITUTION:A MOVE instruction orders that the data designated by an address A for instance is transferred to the region designated by an address B by an extent of length L. Both the fetch address A and the store address B given from a CPU and set to registers 3 and 4 exist at a tag part 10 of a buffer memory. In such case, a normal process is carried out. In case no address A exists at the part 10, a read request and the address A are sent to a main memory. At the same time, the address A is compared 9 with the address B. On the other hand, the result obtained by subtracting 15 the register 3 from the length L is compared 16 with the length of a line. As a result, the data read out of the address A of a main memory is written into the address B or an idle set.
JP10555180A 1980-07-31 1980-07-31 Buffer memory control system Pending JPS5733476A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10555180A JPS5733476A (en) 1980-07-31 1980-07-31 Buffer memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10555180A JPS5733476A (en) 1980-07-31 1980-07-31 Buffer memory control system

Publications (1)

Publication Number Publication Date
JPS5733476A true JPS5733476A (en) 1982-02-23

Family

ID=14410698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10555180A Pending JPS5733476A (en) 1980-07-31 1980-07-31 Buffer memory control system

Country Status (1)

Country Link
JP (1) JPS5733476A (en)

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