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JPS5727322A - Input and output controlling system of computer - Google Patents

Input and output controlling system of computer

Info

Publication number
JPS5727322A
JPS5727322A JP10116680A JP10116680A JPS5727322A JP S5727322 A JPS5727322 A JP S5727322A JP 10116680 A JP10116680 A JP 10116680A JP 10116680 A JP10116680 A JP 10116680A JP S5727322 A JPS5727322 A JP S5727322A
Authority
JP
Japan
Prior art keywords
cpu
input
nonpackaging
control system
computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10116680A
Other languages
Japanese (ja)
Inventor
Yukio Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10116680A priority Critical patent/JPS5727322A/en
Publication of JPS5727322A publication Critical patent/JPS5727322A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To prevent the occurrence of system down in spite of the case in which a CPU accesses a nonpackaged input and output device by mistake with a system using a tag response control system by connecting a specific nonpackaging reporting circuit to a common bus. CONSTITUTION:In the case of accessing a central processing unit CPU, and an input and output device (I/O) 3, the access is started by responding and outputting the signal indicating the receipt of the signal generated by a CPU 1 by said I/O to the CPU 1. A nonpackaging reporting circuit 5 reporting the signal indicating the nonpackaging of the corresponding I/O to the CPU 1 at the point of the time when the timer provided in the inside exceeds a predetermined value when the I/O 3 which the CPU 1 is going to access is not packaged is connected to the common bus 4 of the input and output control system of a computer using such tag response control system.
JP10116680A 1980-07-25 1980-07-25 Input and output controlling system of computer Pending JPS5727322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10116680A JPS5727322A (en) 1980-07-25 1980-07-25 Input and output controlling system of computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10116680A JPS5727322A (en) 1980-07-25 1980-07-25 Input and output controlling system of computer

Publications (1)

Publication Number Publication Date
JPS5727322A true JPS5727322A (en) 1982-02-13

Family

ID=14293437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10116680A Pending JPS5727322A (en) 1980-07-25 1980-07-25 Input and output controlling system of computer

Country Status (1)

Country Link
JP (1) JPS5727322A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58144930A (en) * 1982-02-24 1983-08-29 Fujitsu Ltd Bus monitoring system
JPS59202527A (en) * 1983-05-02 1984-11-16 Fuji Electric Co Ltd Bus control system
JPS61214011A (en) * 1985-03-20 1986-09-22 Res Dev Corp Of Japan Mobile iron piece type electromagnet actuator
JPS61216009A (en) * 1985-03-22 1986-09-25 Res Dev Corp Of Japan Moving iron core type electromagnet actuator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58144930A (en) * 1982-02-24 1983-08-29 Fujitsu Ltd Bus monitoring system
JPS59202527A (en) * 1983-05-02 1984-11-16 Fuji Electric Co Ltd Bus control system
JPS61214011A (en) * 1985-03-20 1986-09-22 Res Dev Corp Of Japan Mobile iron piece type electromagnet actuator
JPS61216009A (en) * 1985-03-22 1986-09-25 Res Dev Corp Of Japan Moving iron core type electromagnet actuator

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