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JPS5725748A - Start-stop synchronizing system - Google Patents

Start-stop synchronizing system

Info

Publication number
JPS5725748A
JPS5725748A JP10102780A JP10102780A JPS5725748A JP S5725748 A JPS5725748 A JP S5725748A JP 10102780 A JP10102780 A JP 10102780A JP 10102780 A JP10102780 A JP 10102780A JP S5725748 A JPS5725748 A JP S5725748A
Authority
JP
Japan
Prior art keywords
circuit
synchronous character
sampling
value
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10102780A
Other languages
Japanese (ja)
Inventor
Sumio Uchiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP10102780A priority Critical patent/JPS5725748A/en
Publication of JPS5725748A publication Critical patent/JPS5725748A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/10—Arrangements for initial synchronisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To realize an automatic correction for the speed of synchronization at the receiver side, by sending a synchronous character from the transmitter side and prior to the transmission of data. CONSTITUTION:A start bit detecting circuit 1 detects the fall of a start bit ST in a transmited signal (a) and then starts counters 3 and 4. The value of the counter 3 shows the time width of the bit ST; and the value of an integrating circuit 5 that adds the count value of the counter 4 shows the time width of the number of bits of a synchronous character plus one. When a synchronous character detecting circuit 7 identifies that the input signal (a) is equal to a synchronous character, the circuit 5 obtains a sampling period (d) of the input data from the integral value and gives it to a sampling circuit 6. At the same time, the circuit 6 receives a synchronous character detection signal (e) from the circuit 7 and carries out a sampling of the input data based on the synchronization of sampling until the next synchronous character is received.
JP10102780A 1980-07-23 1980-07-23 Start-stop synchronizing system Pending JPS5725748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10102780A JPS5725748A (en) 1980-07-23 1980-07-23 Start-stop synchronizing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10102780A JPS5725748A (en) 1980-07-23 1980-07-23 Start-stop synchronizing system

Publications (1)

Publication Number Publication Date
JPS5725748A true JPS5725748A (en) 1982-02-10

Family

ID=14289699

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10102780A Pending JPS5725748A (en) 1980-07-23 1980-07-23 Start-stop synchronizing system

Country Status (1)

Country Link
JP (1) JPS5725748A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61169956A (en) * 1985-01-23 1986-07-31 Fujitsu Ltd Synchronizing system of data transfer speed
EP0315549A2 (en) * 1987-11-06 1989-05-10 Fujitsu Limited Protocol control circuit for data bus system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61169956A (en) * 1985-01-23 1986-07-31 Fujitsu Ltd Synchronizing system of data transfer speed
EP0315549A2 (en) * 1987-11-06 1989-05-10 Fujitsu Limited Protocol control circuit for data bus system

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