JPS57212539A - Arithmetic device - Google Patents
Arithmetic deviceInfo
- Publication number
- JPS57212539A JPS57212539A JP56098016A JP9801681A JPS57212539A JP S57212539 A JPS57212539 A JP S57212539A JP 56098016 A JP56098016 A JP 56098016A JP 9801681 A JP9801681 A JP 9801681A JP S57212539 A JPS57212539 A JP S57212539A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- time
- operating
- comparing
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1497—Details of time redundant execution on a single processing unit
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Retry When Errors Occur (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To reduce the quantity of hardware remarkably comparing with a conventional device, by doubling on a time base in order to obtain an operation result with high reliability by an arithmetic device whose operation result is not changed even if at least 2 variables are exchanged with each other. CONSTITUTION:Variables (x), (y) are inputted to an operating circuit 4 through connecting lines 106, 107 and switching circuit 5, 6, respectively. Its operation result is provided to a degenerating circuit 7, and its degenerated data is provided to a holding circuit 8 and a coparing circuit 9. During an operating time T1, ''0'' is outputted from the comparing circuit 9, and an output of an AND circuit 10 becomes logical ''0''. Subsequently, after the time T1 has passed, during an operating action check time T2, a test signal of logical ''1'' is applied to this device through a connecting line 114. When this test signal is applied to switching circuits 5, 6, the variables (x) (y) are exchanged with time of the time T1, are inputted to the operating circuit 4, are inputted to the holding circuit 8, and the holding circuit 8 provides a data during the time T1 to the comparing circuit 9. Accordingly, the comparing circuit 9 decides its result by a data of a real time of the time T2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56098016A JPS57212539A (en) | 1981-06-24 | 1981-06-24 | Arithmetic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56098016A JPS57212539A (en) | 1981-06-24 | 1981-06-24 | Arithmetic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57212539A true JPS57212539A (en) | 1982-12-27 |
| JPS6116092B2 JPS6116092B2 (en) | 1986-04-28 |
Family
ID=14208030
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56098016A Granted JPS57212539A (en) | 1981-06-24 | 1981-06-24 | Arithmetic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57212539A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03129523A (en) * | 1989-07-11 | 1991-06-03 | Tandem Comput Inc | Method and device for processing data |
| JP2012194599A (en) * | 2011-03-14 | 2012-10-11 | Nec Corp | Arithmetic unit and error detection method |
-
1981
- 1981-06-24 JP JP56098016A patent/JPS57212539A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03129523A (en) * | 1989-07-11 | 1991-06-03 | Tandem Comput Inc | Method and device for processing data |
| JP2012194599A (en) * | 2011-03-14 | 2012-10-11 | Nec Corp | Arithmetic unit and error detection method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6116092B2 (en) | 1986-04-28 |
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