[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS57187730A - Direct memory access system - Google Patents

Direct memory access system

Info

Publication number
JPS57187730A
JPS57187730A JP7257881A JP7257881A JPS57187730A JP S57187730 A JPS57187730 A JP S57187730A JP 7257881 A JP7257881 A JP 7257881A JP 7257881 A JP7257881 A JP 7257881A JP S57187730 A JPS57187730 A JP S57187730A
Authority
JP
Japan
Prior art keywords
address
data
memory access
bus
direct memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7257881A
Other languages
Japanese (ja)
Inventor
Yoshiharu Kamio
Masato Fujisawa
Kazuhiro Sato
Shoji Nojiri
Yoshikazu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7257881A priority Critical patent/JPS57187730A/en
Publication of JPS57187730A publication Critical patent/JPS57187730A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/287—Multiplexed DMA

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To avoid the interruption and the stop of processings of a processing device due to the memory access, by utilizing the fact that a common bus is idle when the processing is executed in the processing device and executing the memory access in this execution time. CONSTITUTION:When the request of the direct memory access (DMA) is requested from an input/output device IOD1, an address of a main storage device MM to be accessed and data to be stored in this address are sent to an address generating circuit A and a data transmitting and receiving circuit D respectively and are held there. When a common bus becomes idle, signal ''1'' is inputted to enable terminals E of circuits A and D, and these circuits are activated to transmit held address information and data to an address bus AB and a data bus DB respectively. The main storage device MM receives these address information and data to store this data in this address.
JP7257881A 1981-05-14 1981-05-14 Direct memory access system Pending JPS57187730A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7257881A JPS57187730A (en) 1981-05-14 1981-05-14 Direct memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7257881A JPS57187730A (en) 1981-05-14 1981-05-14 Direct memory access system

Publications (1)

Publication Number Publication Date
JPS57187730A true JPS57187730A (en) 1982-11-18

Family

ID=13493400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7257881A Pending JPS57187730A (en) 1981-05-14 1981-05-14 Direct memory access system

Country Status (1)

Country Link
JP (1) JPS57187730A (en)

Similar Documents

Publication Publication Date Title
JPS57105879A (en) Control system for storage device
SE8206640L (en) MULTI-TREATMENT SWITCH DEVICE
KR900005287A (en) Data control device and system using it
GB1170587A (en) Data Processing System
JPS56110125A (en) Data processing device
JPS57187730A (en) Direct memory access system
JPS56149629A (en) Information processor
JPS576480A (en) Buffer memory control system
JPS6478361A (en) Data processing system
JPS56168254A (en) Advance control system for input/output control unit
JPS56118165A (en) Processor of video information
JPS55105884A (en) Address conversion device
JPS56118164A (en) Processor of video information
JPS55108068A (en) Memory control system
JPS5783864A (en) Multiprocessor system
JPS5733472A (en) Memory access control system
SU554534A1 (en) Device for interfacing a peripheral system with an electronic computer
JPS5622157A (en) Process system multiplexing system
JPS5750378A (en) Control system of data processor
JPS56143069A (en) Bus coupling system
JPS56103747A (en) Information processing system
JPS5659339A (en) Input/output control unit
JPS56168256A (en) Data processor
JPS5745659A (en) Memory address managing device
JPS6442763A (en) Interrupting system between processors