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JPS57157365A - Busy control system of memory controller - Google Patents

Busy control system of memory controller

Info

Publication number
JPS57157365A
JPS57157365A JP4374381A JP4374381A JPS57157365A JP S57157365 A JPS57157365 A JP S57157365A JP 4374381 A JP4374381 A JP 4374381A JP 4374381 A JP4374381 A JP 4374381A JP S57157365 A JPS57157365 A JP S57157365A
Authority
JP
Japan
Prior art keywords
address
inputted
pipeline
circuit
main storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4374381A
Other languages
Japanese (ja)
Other versions
JPS6049952B2 (en
Inventor
Mikio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4374381A priority Critical patent/JPS6049952B2/en
Publication of JPS57157365A publication Critical patent/JPS57157365A/en
Publication of JPS6049952B2 publication Critical patent/JPS6049952B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To simplify the control, by constituting so that a store address can be inputted to only a reset address pipeline in case of starting the store access by partial write, and an address of the next fetch cycle can be inputted to an address pipeline. CONSTITUTION:A port 11 for setting a main storage access request, a priority circuit 12 for starting the access in accordance with a prescribed priority rank, and a busy display means 13 having plural busy flop-flops corresponding to each bank of the main storage by one to one are provided on the main storage controller. In this state, in case of partial write, after the fetch cycle has been started, an address outputted by the circuit 12 is inputted to an address pipeline 14, an address outputted thereafter is inputted to the circuit 12 for the store cycle, also the reinput to the pipeline 14 is inhibited, moreover the bank address part of its address is inputted to a reset address pipeline 15, and in case of full write and read-out of a data, the bank address part in the output address of the circuit 12 is inputted to the pipeline 15.
JP4374381A 1981-03-24 1981-03-24 Busy control method of memory control device Expired JPS6049952B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4374381A JPS6049952B2 (en) 1981-03-24 1981-03-24 Busy control method of memory control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4374381A JPS6049952B2 (en) 1981-03-24 1981-03-24 Busy control method of memory control device

Publications (2)

Publication Number Publication Date
JPS57157365A true JPS57157365A (en) 1982-09-28
JPS6049952B2 JPS6049952B2 (en) 1985-11-06

Family

ID=12672240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4374381A Expired JPS6049952B2 (en) 1981-03-24 1981-03-24 Busy control method of memory control device

Country Status (1)

Country Link
JP (1) JPS6049952B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258141A (en) * 1988-08-24 1990-02-27 Fujitsu Ltd Memory busy check method
JPH02222047A (en) * 1989-02-23 1990-09-04 Nec Corp Memory controller
JPH02235154A (en) * 1989-03-09 1990-09-18 Nec Corp Memory control unit
EP0465847A2 (en) * 1990-06-11 1992-01-15 Nec Corporation Memory access control having commonly shared pipeline structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258141A (en) * 1988-08-24 1990-02-27 Fujitsu Ltd Memory busy check method
JPH02222047A (en) * 1989-02-23 1990-09-04 Nec Corp Memory controller
JPH02235154A (en) * 1989-03-09 1990-09-18 Nec Corp Memory control unit
EP0465847A2 (en) * 1990-06-11 1992-01-15 Nec Corporation Memory access control having commonly shared pipeline structure
JPH0444136A (en) * 1990-06-11 1992-02-13 Nec Corp Memory access controller

Also Published As

Publication number Publication date
JPS6049952B2 (en) 1985-11-06

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