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JPS57120297A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS57120297A
JPS57120297A JP617381A JP617381A JPS57120297A JP S57120297 A JPS57120297 A JP S57120297A JP 617381 A JP617381 A JP 617381A JP 617381 A JP617381 A JP 617381A JP S57120297 A JPS57120297 A JP S57120297A
Authority
JP
Japan
Prior art keywords
erasure
gate
source
line
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP617381A
Other languages
Japanese (ja)
Other versions
JPS6152555B2 (en
Inventor
Fujio Masuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP617381A priority Critical patent/JPS57120297A/en
Priority to US06/320,937 priority patent/US4437174A/en
Publication of JPS57120297A publication Critical patent/JPS57120297A/en
Publication of JPS6152555B2 publication Critical patent/JPS6152555B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain a device which performs bit-by-bit erasure and never discharges electrons from one floating gate to much, by constituting each memory cell by providing an erasure gate successively to the floating gate of a double gate type MOST. CONSTITUTION:A memory matrix of memory cells M each consisting of a control gate CG, an erasure gate EG, a floating gate FG, a source S, and a drain D has row lines 45 and erasure lines 50. Further, this device is provided with a means of setting the potential of the row line of a selected cell to a low level during erasure, that of applying a high-level erasure voltage to the erasure line of the selected cell during the erasure, that of setting the potentials of respective row lines to the low level during erasure detection, that of giving a prescribed potential difference between the source and drain of the selected cell during the erasure detection, and that of inhibiting the application of the erasure voltage to the erasure line of the cell when detecting the source-drain current of the cell during erasure detection.
JP617381A 1981-01-19 1981-01-19 Semiconductor storage device Granted JPS57120297A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP617381A JPS57120297A (en) 1981-01-19 1981-01-19 Semiconductor storage device
US06/320,937 US4437174A (en) 1981-01-19 1981-11-13 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP617381A JPS57120297A (en) 1981-01-19 1981-01-19 Semiconductor storage device

Publications (2)

Publication Number Publication Date
JPS57120297A true JPS57120297A (en) 1982-07-27
JPS6152555B2 JPS6152555B2 (en) 1986-11-13

Family

ID=11631150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP617381A Granted JPS57120297A (en) 1981-01-19 1981-01-19 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS57120297A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62188099A (en) * 1986-02-13 1987-08-17 Toshiba Corp Electrically erasable and rewritable type semiconductor memory
JPH02276095A (en) * 1988-12-28 1990-11-09 Toshiba Corp Nonvolatile semiconductor memory device
US5708285A (en) * 1994-09-13 1998-01-13 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor information storage device
US5844842A (en) * 1989-02-06 1998-12-01 Hitachi, Ltd. Nonvolatile semiconductor memory device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62188099A (en) * 1986-02-13 1987-08-17 Toshiba Corp Electrically erasable and rewritable type semiconductor memory
JPH02276095A (en) * 1988-12-28 1990-11-09 Toshiba Corp Nonvolatile semiconductor memory device
US6259629B1 (en) 1989-02-06 2001-07-10 Hitachi, Ltd. Nonvolatile semiconductor memory device
US5844842A (en) * 1989-02-06 1998-12-01 Hitachi, Ltd. Nonvolatile semiconductor memory device
US6157576A (en) * 1989-02-06 2000-12-05 Hitachi, Ltd. Nonvolatile semiconductor memory device
US6181600B1 (en) 1989-02-06 2001-01-30 Hitachi, Ltd Nonvolatile semiconductor memory device
US6438036B2 (en) 1989-02-06 2002-08-20 Hitachi, Ltd. Nonvolatile semiconductor memory device
US6747902B2 (en) 1989-02-06 2004-06-08 Renesas Technology Corp. Nonvolatile semiconductor memory apparatus
US6791882B2 (en) 1989-02-06 2004-09-14 Renesas Technology Corp. Nonvolatile semiconductor memory device
US7020028B2 (en) 1989-02-06 2006-03-28 Renesas Technology Corp. Nonvolatile semiconductor memory device
US7099199B2 (en) 1989-02-06 2006-08-29 Renesas Technology Corp. Nonvolatile semiconductor memory device
US7372741B2 (en) 1989-02-06 2008-05-13 Renesas Technology Corp. Nonvolatile memory apparatus having a processor and plural memories one or more of which is a nonvolatile memory having circuitry which performs an erase operation and an erase verify operation when the processor specifies the erase operation mode to the nonvolatile memory
US5708285A (en) * 1994-09-13 1998-01-13 Mitsubishi Denki Kabushiki Kaisha Non-volatile semiconductor information storage device

Also Published As

Publication number Publication date
JPS6152555B2 (en) 1986-11-13

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