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JPS57124990A - Data transmission control system - Google Patents

Data transmission control system

Info

Publication number
JPS57124990A
JPS57124990A JP56011171A JP1117181A JPS57124990A JP S57124990 A JPS57124990 A JP S57124990A JP 56011171 A JP56011171 A JP 56011171A JP 1117181 A JP1117181 A JP 1117181A JP S57124990 A JPS57124990 A JP S57124990A
Authority
JP
Japan
Prior art keywords
address
data
line
memory
data transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56011171A
Other languages
Japanese (ja)
Other versions
JPS637720B2 (en
Inventor
Kazuo Imai
Kenichi Yukimatsu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56011171A priority Critical patent/JPS57124990A/en
Publication of JPS57124990A publication Critical patent/JPS57124990A/en
Publication of JPS637720B2 publication Critical patent/JPS637720B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To save limination of allocation of buffer areas and to reduce the load for a processor to start data transmission, by setting a link address to the 2nd data to the most end of the 1st data. CONSTITUTION:In transmitting data, a head address (n) of a storage area of data to be transmitted is written in an address tj of a line memory 10. The address tj of the line memory 10 is read out at time slot of Tj, and after the content of the address (n) of a transmission buffer memory 1 is set to a register 5, operational processing is made at a signal transmission operating circuit 13 and it is given to a line LN. When succeeding data is present, ''1'' is added to the (n) at an addition circuit, and n+1 is stored to the address tj of the line memory 10. At the time slot of the next line LN, the content of the address n+1 of the memory 1 is similarly transmitted to the line LN. Thus, similar operations is made at the presence of data.
JP56011171A 1981-01-27 1981-01-27 Data transmission control system Granted JPS57124990A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56011171A JPS57124990A (en) 1981-01-27 1981-01-27 Data transmission control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56011171A JPS57124990A (en) 1981-01-27 1981-01-27 Data transmission control system

Publications (2)

Publication Number Publication Date
JPS57124990A true JPS57124990A (en) 1982-08-04
JPS637720B2 JPS637720B2 (en) 1988-02-18

Family

ID=11770599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56011171A Granted JPS57124990A (en) 1981-01-27 1981-01-27 Data transmission control system

Country Status (1)

Country Link
JP (1) JPS57124990A (en)

Also Published As

Publication number Publication date
JPS637720B2 (en) 1988-02-18

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