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JPS57111873A - Multi-address memory circuit - Google Patents

Multi-address memory circuit

Info

Publication number
JPS57111873A
JPS57111873A JP55189307A JP18930780A JPS57111873A JP S57111873 A JPS57111873 A JP S57111873A JP 55189307 A JP55189307 A JP 55189307A JP 18930780 A JP18930780 A JP 18930780A JP S57111873 A JPS57111873 A JP S57111873A
Authority
JP
Japan
Prior art keywords
address
ram51
gate
bit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55189307A
Other languages
Japanese (ja)
Inventor
Shigeo Kurachi
Yoshio Yagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP55189307A priority Critical patent/JPS57111873A/en
Publication of JPS57111873A publication Critical patent/JPS57111873A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To enhance the function of a computer, by producing a multi-address memory system which is suited to a microcomputer, etc. which has high efficiency and a low price. CONSTITUTION:In the normal application mode, an address gate 54 for subject of alteration is opened and the CPU addresses #8(bit 8')-#15(bit 15) are used for the addresses of an RAM51 as they are. At the same time, the terminals CS and RD of the RAM51 are selected through OR circuits 57 and 58 plus an AND circuit 60 respectivey. Thus the RAM51 is read. When the cnverting contents of the address is altered, a flip-flop 6 is reset by the address on a data bus. Thus a contents altering address gate 52, a two-way data bus gate 55 and an AND circuit 59 are opened, and a decoder 56 is selected by the state of the address.
JP55189307A 1980-12-27 1980-12-27 Multi-address memory circuit Pending JPS57111873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55189307A JPS57111873A (en) 1980-12-27 1980-12-27 Multi-address memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55189307A JPS57111873A (en) 1980-12-27 1980-12-27 Multi-address memory circuit

Publications (1)

Publication Number Publication Date
JPS57111873A true JPS57111873A (en) 1982-07-12

Family

ID=16239142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55189307A Pending JPS57111873A (en) 1980-12-27 1980-12-27 Multi-address memory circuit

Country Status (1)

Country Link
JP (1) JPS57111873A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128037A (en) * 1982-01-22 1983-07-30 Sharp Corp Magnetooptical head

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58128037A (en) * 1982-01-22 1983-07-30 Sharp Corp Magnetooptical head
JPH0338663B2 (en) * 1982-01-22 1991-06-11 Sharp Kk

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