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JPS57114950A - Loop processing system for program controller - Google Patents

Loop processing system for program controller

Info

Publication number
JPS57114950A
JPS57114950A JP141381A JP141381A JPS57114950A JP S57114950 A JPS57114950 A JP S57114950A JP 141381 A JP141381 A JP 141381A JP 141381 A JP141381 A JP 141381A JP S57114950 A JPS57114950 A JP S57114950A
Authority
JP
Japan
Prior art keywords
instruction
loop
address
register
data operation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP141381A
Other languages
Japanese (ja)
Inventor
Michihiro Yamane
Yoshitaka Kitano
Tominobu Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP141381A priority Critical patent/JPS57114950A/en
Publication of JPS57114950A publication Critical patent/JPS57114950A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To enable high speed D0 loop, by adding one bit designating the presence of address alteration in a DO loop to a data operation instruction and providing a register storing an address. CONSTITUTION:If an instruction fetched from a program memory 6 to an instruction register 7 is a DO instruction, a program counter 4 and a register 5 are separated to store the address of the DO instruction in the register 5. The processing instruction in the DO loop is sequentially executed and the instruction comes to an address m-1. The final bit of the data operation instruction in the DO loop is set to 1 in advance. Thus, an address calculation circuit 8 folds the progress of the program to the address assured in the register 5, and unconditional jump of the DO loop to the head instruction is executed in parallel with the data operation of the instruction of m being the final instruction of the loop, allowing to reduce the machine cycle required for the execution of the unconditional jump.
JP141381A 1981-01-08 1981-01-08 Loop processing system for program controller Pending JPS57114950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP141381A JPS57114950A (en) 1981-01-08 1981-01-08 Loop processing system for program controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP141381A JPS57114950A (en) 1981-01-08 1981-01-08 Loop processing system for program controller

Publications (1)

Publication Number Publication Date
JPS57114950A true JPS57114950A (en) 1982-07-17

Family

ID=11500792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP141381A Pending JPS57114950A (en) 1981-01-08 1981-01-08 Loop processing system for program controller

Country Status (1)

Country Link
JP (1) JPS57114950A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607536A (en) * 1983-06-24 1985-01-16 Mitsubishi Electric Corp Information processor
JPS60132242A (en) * 1983-12-20 1985-07-15 Matsushita Electric Ind Co Ltd Program control device
US4787065A (en) * 1984-03-13 1988-11-22 Telecommunications Radioelectriquetes Et Telephomiques T.R.T. Data processing apparatus providing cyclic addressing of a data store in selectively opposite directions
US4937738A (en) * 1984-08-31 1990-06-26 Hitachi, Ltd. Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction
FR2693572A1 (en) * 1992-07-13 1994-01-14 Texas Instruments France Handling program loops in microprocessor data processing system
WO1994002894A2 (en) * 1992-07-13 1994-02-03 Texas Instruments France Data-processing system with a device for handling program loops
US5452425A (en) * 1989-10-13 1995-09-19 Texas Instruments Incorporated Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words
US5507027A (en) * 1993-12-28 1996-04-09 Mitsubishi Denki Kabushiki Kaisha Pipeline processor with hardware loop function using instruction address stack for holding content of program counter and returning the content back to program counter
JP2008079416A (en) * 2006-09-21 2008-04-03 Toshiba Corp Mica tape winding property evaluation method and device

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607536A (en) * 1983-06-24 1985-01-16 Mitsubishi Electric Corp Information processor
JPH0214730B2 (en) * 1983-06-24 1990-04-09 Mitsubishi Electric Corp
JPS60132242A (en) * 1983-12-20 1985-07-15 Matsushita Electric Ind Co Ltd Program control device
JPS6359174B2 (en) * 1983-12-20 1988-11-18
US4787065A (en) * 1984-03-13 1988-11-22 Telecommunications Radioelectriquetes Et Telephomiques T.R.T. Data processing apparatus providing cyclic addressing of a data store in selectively opposite directions
US4937738A (en) * 1984-08-31 1990-06-26 Hitachi, Ltd. Data processing system which selectively bypasses a cache memory in fetching information based upon bit information of an instruction
US5452425A (en) * 1989-10-13 1995-09-19 Texas Instruments Incorporated Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words
FR2693572A1 (en) * 1992-07-13 1994-01-14 Texas Instruments France Handling program loops in microprocessor data processing system
WO1994002894A2 (en) * 1992-07-13 1994-02-03 Texas Instruments France Data-processing system with a device for handling program loops
WO1994002894A3 (en) * 1992-07-13 1994-05-11 Data-processing system with a device for handling program loops
US5507027A (en) * 1993-12-28 1996-04-09 Mitsubishi Denki Kabushiki Kaisha Pipeline processor with hardware loop function using instruction address stack for holding content of program counter and returning the content back to program counter
JP2008079416A (en) * 2006-09-21 2008-04-03 Toshiba Corp Mica tape winding property evaluation method and device

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