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JPS5696338A - Interrupt processing method of microcomputer - Google Patents

Interrupt processing method of microcomputer

Info

Publication number
JPS5696338A
JPS5696338A JP17209979A JP17209979A JPS5696338A JP S5696338 A JPS5696338 A JP S5696338A JP 17209979 A JP17209979 A JP 17209979A JP 17209979 A JP17209979 A JP 17209979A JP S5696338 A JPS5696338 A JP S5696338A
Authority
JP
Japan
Prior art keywords
interrupt
level
microcomputer
signal
interrupt processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17209979A
Other languages
Japanese (ja)
Inventor
Tsutomu Kaneda
Hiroshi Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP17209979A priority Critical patent/JPS5696338A/en
Publication of JPS5696338A publication Critical patent/JPS5696338A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To simplify the program of the interrupt processing and prevent malfunctions, by inputting two or more interrupt signals to the FF to decide the level of the output signal when two or more interrupt signals are input.
CONSTITUTION: In case that interrupt signal A becomes 0-level to cause an interrupt, the output of AND gate 4 becomes 0, and microcomputer 3 enters from the main program to the interrupt processing routine. Meanwhile, since FF5 is set and level 1 is held in input terminal I0 because interrupt signal A is 0-level, microcomputer 3 decides that the interrupt has been performed by interrupt signal A. When interrupt signal B becomes 0-level, FF5 is reset by interrupt signal B, and level 0 is applied to input terminal I0, and therefore, it is decided that the interrupt has been performed by interrupt signal B, and microcomputer 3 executes the interrupt processing routine corresponding to it.
COPYRIGHT: (C)1981,JPO&Japio
JP17209979A 1979-12-28 1979-12-28 Interrupt processing method of microcomputer Pending JPS5696338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17209979A JPS5696338A (en) 1979-12-28 1979-12-28 Interrupt processing method of microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17209979A JPS5696338A (en) 1979-12-28 1979-12-28 Interrupt processing method of microcomputer

Publications (1)

Publication Number Publication Date
JPS5696338A true JPS5696338A (en) 1981-08-04

Family

ID=15935516

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17209979A Pending JPS5696338A (en) 1979-12-28 1979-12-28 Interrupt processing method of microcomputer

Country Status (1)

Country Link
JP (1) JPS5696338A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63137313A (en) * 1986-11-29 1988-06-09 Sharp Corp Computer equipment

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131731A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Interruption circuit for computer

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53131731A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Interruption circuit for computer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63137313A (en) * 1986-11-29 1988-06-09 Sharp Corp Computer equipment
JPH0511324B2 (en) * 1986-11-29 1993-02-15 Sharp Kk

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