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JPS5693406A - Differential amplifier - Google Patents

Differential amplifier

Info

Publication number
JPS5693406A
JPS5693406A JP17332479A JP17332479A JPS5693406A JP S5693406 A JPS5693406 A JP S5693406A JP 17332479 A JP17332479 A JP 17332479A JP 17332479 A JP17332479 A JP 17332479A JP S5693406 A JPS5693406 A JP S5693406A
Authority
JP
Japan
Prior art keywords
channel
commonly
gate
series
pair
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17332479A
Other languages
Japanese (ja)
Inventor
Tatsuji Asakawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP17332479A priority Critical patent/JPS5693406A/en
Publication of JPS5693406A publication Critical patent/JPS5693406A/en
Pending legal-status Critical Current

Links

Landscapes

  • Amplifiers (AREA)

Abstract

PURPOSE: To make the bias circuit needless and reduce power consumption, by using the depletion mode transistor as the constant-current source transistor and by connecting the gate and the source commonly.
CONSTITUTION: A pair of differential input MISFETs 24 and 25 of the same polarity are connected in series to depletion mode N-channel MISFET23 which has the gate and the source connected commonly. Further, a pair of enhancement mode P-channel load MISFETs 26 and 27 of the opposite polarity which have gates connected commonly to the drain of MISFET26 are connected in series to a pair of FETs 24 and 25 to form differential amplification stage B. The output of this differential amplification stage B is taken out from the drain common connection point of FETs 25 and 27 and is amplified by amplification stage C, where enhance mode P-channel MISFET 28 and depletion mode N-channel MISFET29 have the gate and the source connected commonly are connected in series, and is output.
COPYRIGHT: (C)1981,JPO&Japio
JP17332479A 1979-12-26 1979-12-26 Differential amplifier Pending JPS5693406A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17332479A JPS5693406A (en) 1979-12-26 1979-12-26 Differential amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17332479A JPS5693406A (en) 1979-12-26 1979-12-26 Differential amplifier

Publications (1)

Publication Number Publication Date
JPS5693406A true JPS5693406A (en) 1981-07-29

Family

ID=15958314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17332479A Pending JPS5693406A (en) 1979-12-26 1979-12-26 Differential amplifier

Country Status (1)

Country Link
JP (1) JPS5693406A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4745305A (en) * 1985-09-23 1988-05-17 Ncr Corporation Common cell I/O interface circuit
WO1992004770A1 (en) * 1990-09-12 1992-03-19 Fujitsu Limited Differential amplifying circuit of operational amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4745305A (en) * 1985-09-23 1988-05-17 Ncr Corporation Common cell I/O interface circuit
WO1992004770A1 (en) * 1990-09-12 1992-03-19 Fujitsu Limited Differential amplifying circuit of operational amplifier

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