JPS5689125A - Binary circuit - Google Patents
Binary circuitInfo
- Publication number
- JPS5689125A JPS5689125A JP16658079A JP16658079A JPS5689125A JP S5689125 A JPS5689125 A JP S5689125A JP 16658079 A JP16658079 A JP 16658079A JP 16658079 A JP16658079 A JP 16658079A JP S5689125 A JPS5689125 A JP S5689125A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- output signal
- comparator
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To make the input signal binary accurately, by outputting the AND output between the output signal of the first comparator and the OR output between the output signal of the third comparator and the output signal of the monostable multivibrator. CONSTITUTION:When signal (a) is input, signal (a) is delayed by delay element 1 and becomes signal (b). Signal (b) is delayed furthermore by delay element 2 and becomes signal (c). Circuit block 11 compares signal (b) from delay element 1 with the output signal of the analogue switch (not shown in the figure) to output signal (j). Comparator 16 compares signal (c) from element 2 with signal (k) from attenuating circuit 15, and supplies output signal (l) as a high level to OR gate 17 when signal (c) is larger. AND gate 18 operates AND between output signal (p) of gate 17 and output signal (j) of block 11 and outputs signal (q) as the final binary signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16658079A JPS5689125A (en) | 1979-12-21 | 1979-12-21 | Binary circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16658079A JPS5689125A (en) | 1979-12-21 | 1979-12-21 | Binary circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5689125A true JPS5689125A (en) | 1981-07-20 |
Family
ID=15833900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16658079A Pending JPS5689125A (en) | 1979-12-21 | 1979-12-21 | Binary circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5689125A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS643330U (en) * | 1987-06-23 | 1989-01-10 |
-
1979
- 1979-12-21 JP JP16658079A patent/JPS5689125A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS643330U (en) * | 1987-06-23 | 1989-01-10 |
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