JPS5652438A - Decoding circuit - Google Patents

Abstract

PURPOSE:To obtain a decoding circuit of high-speed processing by use of a few number of parts, by forming the circuit by a counter which presets a low-rank m bit in the binary code of n bit, a decoder which inputs a high-rank (n-m) bits, and a shift register. CONSTITUTION:After the low-rank m(=4) bits in the binary code of the input n (=8) bits have been preset in the counter 220, clock pulses of 2m pieces are input from the terminal 201. If the numerical value which has been preset is made M, at the time of the (2<m>-M)-th input pulse, ripple carry is generated from the Q terminal of the counter, it is input to a decoder 212 which inputs the high-rank (n-m) bits, and it is decoded to signal of 2<(n-m)> pieces and is output. An output signal of the decoder is provided to one series input terminal of the shift registers SR301-316 which have been selected by the (n-m) bits. Thus, a binary code of n bits can be decoded to outputs of 2<m>X2<m> pieces by selecting one SR by the high-rank bit and selecting one output terminal of SR which has been selected by the low-rank bit.