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JPS5647843A - Variable clock frequency computer - Google Patents

Variable clock frequency computer

Info

Publication number
JPS5647843A
JPS5647843A JP12338679A JP12338679A JPS5647843A JP S5647843 A JPS5647843 A JP S5647843A JP 12338679 A JP12338679 A JP 12338679A JP 12338679 A JP12338679 A JP 12338679A JP S5647843 A JPS5647843 A JP S5647843A
Authority
JP
Japan
Prior art keywords
clock frequency
execution
circuit
variable clock
frequency computer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12338679A
Other languages
Japanese (ja)
Inventor
Kazuo Kishimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12338679A priority Critical patent/JPS5647843A/en
Publication of JPS5647843A publication Critical patent/JPS5647843A/en
Pending legal-status Critical Current

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  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE: To make it possible to execute continuous instructions by avoiding waste of time, by performing the operation by the clock frequency which is suitable for each execution cycle.
CONSTITUTION: A digital signal 8 according to the execution time is output to the D/A conversion circuit 5 from the decoding circuit 4, corresponding to classfication of the instruction 7 which is output from the control circuit 1. An optimal clock pulse 9 to the execution cycle based on the above digital signal is generated in the V/F conversion circuit 6, and it is provided to both the control circuit 1 and the operation circuit 2. Thus, waste of the execution time can be avoided by means of execution of the clock frequency which is optimal to each execution cycle.
COPYRIGHT: (C)1981,JPO&Japio
JP12338679A 1979-09-25 1979-09-25 Variable clock frequency computer Pending JPS5647843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12338679A JPS5647843A (en) 1979-09-25 1979-09-25 Variable clock frequency computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12338679A JPS5647843A (en) 1979-09-25 1979-09-25 Variable clock frequency computer

Publications (1)

Publication Number Publication Date
JPS5647843A true JPS5647843A (en) 1981-04-30

Family

ID=14859284

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12338679A Pending JPS5647843A (en) 1979-09-25 1979-09-25 Variable clock frequency computer

Country Status (1)

Country Link
JP (1) JPS5647843A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6081627A (en) * 1983-10-07 1985-05-09 Matsushita Electric Ind Co Ltd Electronic computer device
JPH0462610A (en) * 1990-06-29 1992-02-27 Sharp Corp Data communication equipment
US6519706B1 (en) 1998-10-12 2003-02-11 Nec Corporation DSP control apparatus and method for reducing power consumption

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6081627A (en) * 1983-10-07 1985-05-09 Matsushita Electric Ind Co Ltd Electronic computer device
JPH0462610A (en) * 1990-06-29 1992-02-27 Sharp Corp Data communication equipment
US6519706B1 (en) 1998-10-12 2003-02-11 Nec Corporation DSP control apparatus and method for reducing power consumption

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