[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPS5642362A - Package for integrated circuit - Google Patents

Package for integrated circuit

Info

Publication number
JPS5642362A
JPS5642362A JP11825979A JP11825979A JPS5642362A JP S5642362 A JPS5642362 A JP S5642362A JP 11825979 A JP11825979 A JP 11825979A JP 11825979 A JP11825979 A JP 11825979A JP S5642362 A JPS5642362 A JP S5642362A
Authority
JP
Japan
Prior art keywords
metallized layer
package
dense
forming
porous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11825979A
Other languages
Japanese (ja)
Other versions
JPS605224B2 (en
Inventor
Norio Honda
Masahiro Sugimoto
Hidehiko Akasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11825979A priority Critical patent/JPS605224B2/en
Publication of JPS5642362A publication Critical patent/JPS5642362A/en
Publication of JPS605224B2 publication Critical patent/JPS605224B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance the reliability of the IC by forming a conductive pattern provided on a substrate of a porous metallized layer immersed with low resistance solder in a flat ceramic package and forming the connecting portion with an external lead terminal of double structure of dense and porous metallized layers. CONSTITUTION:When the IC chip 2 is secured into a die cavity 3 formed at a ceramic base 1 forming a flat type ceramic package, it is secured through a dense W metallized layer 13 in normal way. Then, the electrode of the chip 2 is connected to the conductive pattern 31 on the base 1 by using a fine wire 6. At this time the pattern 31 is formed of porous W metallized layer 31 immersed with low resistance silver solder. When connecting an external lead terminal 5 to the end of the pattern 31, a dense W metallized layer 31' is interposed therebetween. Thus, there can be obtained a package of good electric conductivity and adherence.
JP11825979A 1979-09-14 1979-09-14 Packages for integrated circuits Expired JPS605224B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11825979A JPS605224B2 (en) 1979-09-14 1979-09-14 Packages for integrated circuits

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11825979A JPS605224B2 (en) 1979-09-14 1979-09-14 Packages for integrated circuits

Publications (2)

Publication Number Publication Date
JPS5642362A true JPS5642362A (en) 1981-04-20
JPS605224B2 JPS605224B2 (en) 1985-02-08

Family

ID=14732186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11825979A Expired JPS605224B2 (en) 1979-09-14 1979-09-14 Packages for integrated circuits

Country Status (1)

Country Link
JP (1) JPS605224B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5820543U (en) * 1981-08-03 1983-02-08 三洋電機株式会社 Electrodes for soldering thick film circuits
JPS5931043A (en) * 1982-08-12 1984-02-18 Mitsubishi Electric Corp Semiconductor device package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5820543U (en) * 1981-08-03 1983-02-08 三洋電機株式会社 Electrodes for soldering thick film circuits
JPS5931043A (en) * 1982-08-12 1984-02-18 Mitsubishi Electric Corp Semiconductor device package

Also Published As

Publication number Publication date
JPS605224B2 (en) 1985-02-08

Similar Documents

Publication Publication Date Title
JPS58446U (en) Hybrid integrated circuit device
JPS55140251A (en) Semiconductor device
US6847116B2 (en) Chip-type semiconductor light-emitting device
JPS5779652A (en) Resin-sealed semiconductor device
JPS5642362A (en) Package for integrated circuit
JPS56137659A (en) Semiconductor device and its manufacture
JPS6489350A (en) Package for containing semiconductor element
JPS5521154A (en) Ceramic package
JPS57130443A (en) Substrate for hybrid integrated circuit
JPS5575257A (en) Substrate circuit device
JPS5618454A (en) Hybrid integrated circuit
JPS5619648A (en) Package for integrated circuit
JPS5546561A (en) Method of fabricating hybrid integrated circuit
JPS57113261A (en) Semiconductor device
JPS57121239A (en) Semiconductor device
JPS56142659A (en) Semiconductor device
JPS54132166A (en) Socket for semiconductor device
JPS6473610A (en) Composite chip type electronic component and manufacture thereof
JPS5571053A (en) Circuit device
JPS5932148Y2 (en) Chip parts for jumpers
JPS5732660A (en) Semiconductor device
JPS56161664A (en) Manufacture of lead for connecting semiconductor device
JPS5740945A (en) Integrated circuit device
JPS56153754A (en) Power transistor
JPS6459953A (en) Manufacture of compound integrated circuit