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JPS5636147A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS5636147A
JPS5636147A JP11189479A JP11189479A JPS5636147A JP S5636147 A JPS5636147 A JP S5636147A JP 11189479 A JP11189479 A JP 11189479A JP 11189479 A JP11189479 A JP 11189479A JP S5636147 A JPS5636147 A JP S5636147A
Authority
JP
Japan
Prior art keywords
film
wiring
hole portion
lead
opened hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11189479A
Other languages
Japanese (ja)
Other versions
JPS6318335B2 (en
Inventor
Kenzo Hatada
Kosei Kajiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11189479A priority Critical patent/JPS5636147A/en
Publication of JPS5636147A publication Critical patent/JPS5636147A/en
Publication of JPS6318335B2 publication Critical patent/JPS6318335B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate the formation of crossover wiring by a method wherein a lead electrode is made up which crosses an opened hole portion of a film of a film carrier to one side of the opened hole portion from the other side. CONSTITUTION:A continuous Cu lead terminal 31 is formed crossing an opened hole portion 5 of a semiconductor element placing portion of a tape film 3 except Cu lead terminals 4. A semiconductor element 1 is placed on the opened hole portion 5 of the tape film 3, and the semiconductor element 1 and the Cu lead are connected mechanically and electrically. The film tape is cut, and mounted onto a ceramic substrate 11. A fixed electric circuit is constituted in such a manner that a Cu lead terminal 4' is connected to a wiring pattern 12' printed on the ceramic substrate 11, the Cu lead terminal 31 is connected to wiring patterns 13' and 13'', and crossover wiring is formed. Thus, crossover wiring can be made up easily without using multilayer wiring, etc.
JP11189479A 1979-08-31 1979-08-31 Semiconductor device and its manufacture Granted JPS5636147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11189479A JPS5636147A (en) 1979-08-31 1979-08-31 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11189479A JPS5636147A (en) 1979-08-31 1979-08-31 Semiconductor device and its manufacture

Publications (2)

Publication Number Publication Date
JPS5636147A true JPS5636147A (en) 1981-04-09
JPS6318335B2 JPS6318335B2 (en) 1988-04-18

Family

ID=14572797

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11189479A Granted JPS5636147A (en) 1979-08-31 1979-08-31 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPS5636147A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331565U (en) * 1986-08-14 1988-03-01
JPH01181540A (en) * 1988-01-15 1989-07-19 Internatl Business Mach Corp <Ibm> Tab package
JPH02119253A (en) * 1988-10-28 1990-05-07 Nec Corp Hybrid integrated circuit device
WO1996004682A1 (en) * 1994-07-29 1996-02-15 Havant International Limited Electronic circuit package
JP2001209774A (en) * 2000-01-25 2001-08-03 Hitachi Cable Ltd Ic card and its manufacturing method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6331565U (en) * 1986-08-14 1988-03-01
JPH01181540A (en) * 1988-01-15 1989-07-19 Internatl Business Mach Corp <Ibm> Tab package
JPH0534826B2 (en) * 1988-01-15 1993-05-25 Intaanashonaru Bijinesu Mashiinzu Corp
JPH02119253A (en) * 1988-10-28 1990-05-07 Nec Corp Hybrid integrated circuit device
WO1996004682A1 (en) * 1994-07-29 1996-02-15 Havant International Limited Electronic circuit package
JP2001209774A (en) * 2000-01-25 2001-08-03 Hitachi Cable Ltd Ic card and its manufacturing method
JP4529216B2 (en) * 2000-01-25 2010-08-25 凸版印刷株式会社 IC card and manufacturing method thereof

Also Published As

Publication number Publication date
JPS6318335B2 (en) 1988-04-18

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