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JPS5634235A - Logical operation circuit - Google Patents

Logical operation circuit

Info

Publication number
JPS5634235A
JPS5634235A JP11058879A JP11058879A JPS5634235A JP S5634235 A JPS5634235 A JP S5634235A JP 11058879 A JP11058879 A JP 11058879A JP 11058879 A JP11058879 A JP 11058879A JP S5634235 A JPS5634235 A JP S5634235A
Authority
JP
Japan
Prior art keywords
potential
circuit
output
waveform
clamp
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11058879A
Other languages
Japanese (ja)
Inventor
Isamu Takano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11058879A priority Critical patent/JPS5634235A/en
Publication of JPS5634235A publication Critical patent/JPS5634235A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To make it possible to improve the circuit operation speed, by shaping the waveform to be supplied to the next-stage circuit by clamping the output waveform without influence upon the function as a logical operation circuit. CONSTITUTION:Switching element 42 and load element 41 are formed with Schottky barrier FETs, and voltage source 45 to supply a clamp voltage through Schottky barrier diode 44 is connected to this circuit. Then, when input signal A of input terminal 421 changes from the high level to the low level, element 42 is turned off to raise the output potential at output point 422 up to VDD approximately. Under this state, when the potential at output point 422 tries to become a potential higher than the clamp voltage of voltage source 45, diode 44 becomes short-circuited to clamp the output potential of output end 423 at potential A. Thus, the potential of output end 423 is clamped to shape the waveform to be supplied to the next-stage circuit, thereby improving the operation speed of the circuit.
JP11058879A 1979-08-29 1979-08-29 Logical operation circuit Pending JPS5634235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11058879A JPS5634235A (en) 1979-08-29 1979-08-29 Logical operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11058879A JPS5634235A (en) 1979-08-29 1979-08-29 Logical operation circuit

Publications (1)

Publication Number Publication Date
JPS5634235A true JPS5634235A (en) 1981-04-06

Family

ID=14539653

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11058879A Pending JPS5634235A (en) 1979-08-29 1979-08-29 Logical operation circuit

Country Status (1)

Country Link
JP (1) JPS5634235A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491747A (en) * 1981-09-30 1985-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Logic circuit using depletion mode field effect switching transistors
FR2574231A1 (en) * 1984-12-04 1986-06-06 Thomson Csf LOGIC VOLTAGE EXCURSION LIMITER CIRCUIT, AND LOGIC CIRCUIT PROVIDED WITH SUCH EXCURSION LIMITER
JPS63187912A (en) * 1987-01-30 1988-08-03 Yokogawa Hewlett Packard Ltd Pulse shaping device
JPH01228320A (en) * 1988-03-09 1989-09-12 Agency Of Ind Science & Technol Gallium arsenic semiconductor integrated circuit
JP2021082879A (en) * 2019-11-15 2021-05-27 富士電機株式会社 Logic circuit and circuit chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210752B2 (en) * 1972-10-19 1977-03-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5210752B2 (en) * 1972-10-19 1977-03-25

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491747A (en) * 1981-09-30 1985-01-01 Tokyo Shibaura Denki Kabushiki Kaisha Logic circuit using depletion mode field effect switching transistors
FR2574231A1 (en) * 1984-12-04 1986-06-06 Thomson Csf LOGIC VOLTAGE EXCURSION LIMITER CIRCUIT, AND LOGIC CIRCUIT PROVIDED WITH SUCH EXCURSION LIMITER
US4626714A (en) * 1984-12-04 1986-12-02 Thomson-Csf Circuit for limiting the deviation of logic voltages
JPS63187912A (en) * 1987-01-30 1988-08-03 Yokogawa Hewlett Packard Ltd Pulse shaping device
JPH01228320A (en) * 1988-03-09 1989-09-12 Agency Of Ind Science & Technol Gallium arsenic semiconductor integrated circuit
JP2545712B2 (en) * 1988-03-09 1996-10-23 工業技術院長 Gallium arsenide semiconductor integrated circuit
JP2021082879A (en) * 2019-11-15 2021-05-27 富士電機株式会社 Logic circuit and circuit chip

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