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JPS5624646A - Divider - Google Patents

Divider

Info

Publication number
JPS5624646A
JPS5624646A JP10086379A JP10086379A JPS5624646A JP S5624646 A JPS5624646 A JP S5624646A JP 10086379 A JP10086379 A JP 10086379A JP 10086379 A JP10086379 A JP 10086379A JP S5624646 A JPS5624646 A JP S5624646A
Authority
JP
Japan
Prior art keywords
sub
add
time
subtraction
decode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10086379A
Other languages
Japanese (ja)
Other versions
JPS6029408B2 (en
Inventor
Koichi Ueda
Shigemi Uemoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54100863A priority Critical patent/JPS6029408B2/en
Publication of JPS5624646A publication Critical patent/JPS5624646A/en
Publication of JPS6029408B2 publication Critical patent/JPS6029408B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To shorten the required time by composing again so as to operate the circuit element which is operating serially in parallel and retaining the required time necessary for one cycle of the operation under minimum time unit.
CONSTITUTION: In the basic cycle of the divider, the result of the addition and subtraction by ADD/SUB (processing of adder) is not decoded but upper rank 4 bits and DIVISOR upper rank 2 bits of PARTIAL REMAINDER (partial multiplication and division) and SUBSTRACTER (±n times DIVISOR) are directly decoded. In this manner, the decode in DECODE can be started at the time of the same point as the starting point of the addition and subtraction by ADD/SUB and completed at the time of further before the completion point of the addition and subtraction. The correction of the decode is done in SELECT by waiting the carry signal from ADD/SUB and this correction can be completed before the final output time of ADD/SUB.
COPYRIGHT: (C)1981,JPO&Japio
JP54100863A 1979-08-08 1979-08-08 divider Expired JPS6029408B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54100863A JPS6029408B2 (en) 1979-08-08 1979-08-08 divider

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54100863A JPS6029408B2 (en) 1979-08-08 1979-08-08 divider

Publications (2)

Publication Number Publication Date
JPS5624646A true JPS5624646A (en) 1981-03-09
JPS6029408B2 JPS6029408B2 (en) 1985-07-10

Family

ID=14285141

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54100863A Expired JPS6029408B2 (en) 1979-08-08 1979-08-08 divider

Country Status (1)

Country Link
JP (1) JPS6029408B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503512A (en) * 1982-02-22 1985-03-05 Amdahl Corporation Cellular division circuit
JPS617939A (en) * 1984-06-22 1986-01-14 Fujitsu Ltd High radix non-recoverable divider
JPH0218615A (en) * 1988-07-06 1990-01-22 Nec Ic Microcomput Syst Ltd Dividing circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503512A (en) * 1982-02-22 1985-03-05 Amdahl Corporation Cellular division circuit
JPS617939A (en) * 1984-06-22 1986-01-14 Fujitsu Ltd High radix non-recoverable divider
JPH0370252B2 (en) * 1984-06-22 1991-11-07 Fujitsu Ltd
JPH0218615A (en) * 1988-07-06 1990-01-22 Nec Ic Microcomput Syst Ltd Dividing circuit

Also Published As

Publication number Publication date
JPS6029408B2 (en) 1985-07-10

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