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JPS5622289A - Analog memory circuit - Google Patents

Analog memory circuit

Info

Publication number
JPS5622289A
JPS5622289A JP9729479A JP9729479A JPS5622289A JP S5622289 A JPS5622289 A JP S5622289A JP 9729479 A JP9729479 A JP 9729479A JP 9729479 A JP9729479 A JP 9729479A JP S5622289 A JPS5622289 A JP S5622289A
Authority
JP
Japan
Prior art keywords
circuit
output
write
readout
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9729479A
Other languages
Japanese (ja)
Other versions
JPS6160520B2 (en
Inventor
Yasuo Nagai
Koshiro Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9729479A priority Critical patent/JPS5622289A/en
Publication of JPS5622289A publication Critical patent/JPS5622289A/en
Publication of JPS6160520B2 publication Critical patent/JPS6160520B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE: To enable to build in the circuit into monolythic semiconductor integrated circuit, by adding the switch function to the voltage follower circuit consisting of bipolar transistors and using it as the switch means.
CONSTITUTION: When the hold signal H is at low level, transistors Q4, Q5 are off and Q1, Q2 are operated, then the input signal Vin is output as it is, allowing writein to the capacitor C. In this case, the readout circuit has low level of output Vout, with Q7 on and Q6 off. Next, when the signal H is at high, Q4, Q5 are on and the output of the write-in circuit is off both for Q1, Q3. Accordingly, the capacitor C holds the write-in analog level. Further, since Q7 is off in the readout circuit, Q6 is operated and the hold level can be obtained as the output voltage Vout. Similarly, write-in/readout can be made.
COPYRIGHT: (C)1981,JPO&Japio
JP9729479A 1979-08-01 1979-08-01 Analog memory circuit Granted JPS5622289A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9729479A JPS5622289A (en) 1979-08-01 1979-08-01 Analog memory circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9729479A JPS5622289A (en) 1979-08-01 1979-08-01 Analog memory circuit

Publications (2)

Publication Number Publication Date
JPS5622289A true JPS5622289A (en) 1981-03-02
JPS6160520B2 JPS6160520B2 (en) 1986-12-20

Family

ID=14188472

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9729479A Granted JPS5622289A (en) 1979-08-01 1979-08-01 Analog memory circuit

Country Status (1)

Country Link
JP (1) JPS5622289A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59209427A (en) * 1983-05-13 1984-11-28 Tiger Vacuum Bottle Co Ltd Method for forming flat plate to cylindrical form
JP2003529258A (en) * 2000-03-28 2003-09-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Tracking and holding amplifier

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59209427A (en) * 1983-05-13 1984-11-28 Tiger Vacuum Bottle Co Ltd Method for forming flat plate to cylindrical form
JP2003529258A (en) * 2000-03-28 2003-09-30 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Tracking and holding amplifier
JP4923308B2 (en) * 2000-03-28 2012-04-25 エスティー‐エリクソン、ソシエテ、アノニム Tracking and holding amplifier

Also Published As

Publication number Publication date
JPS6160520B2 (en) 1986-12-20

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