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JPS5619599A - Data processor having memory unit - Google Patents

Data processor having memory unit

Info

Publication number
JPS5619599A
JPS5619599A JP9528979A JP9528979A JPS5619599A JP S5619599 A JPS5619599 A JP S5619599A JP 9528979 A JP9528979 A JP 9528979A JP 9528979 A JP9528979 A JP 9528979A JP S5619599 A JPS5619599 A JP S5619599A
Authority
JP
Japan
Prior art keywords
control
memory unit
refreshing
period
patrol
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9528979A
Other languages
Japanese (ja)
Inventor
Hiroshi Nakamura
Motozo Nagano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9528979A priority Critical patent/JPS5619599A/en
Publication of JPS5619599A publication Critical patent/JPS5619599A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To simplify the control for the memory unit, by selecting the period of patrol control suitably and commonly performing the refresh control.
CONSTITUTION: The content of the same address of the segments (1-0)W(1-3) of the memory unit 1 is read out at a bundle with the address information from the patrol control circuit 4, and fed to the data check and correction circuit 6 via the selection circuit 5 for refreshing. Thus, the accessing to the bit on the same line of memory chip means the refreshing of all the bits on the line are performed substantially. Accordingly, the patrol period is selected to the period T' smaller than the refreshing period T predetermined and the refreshing control is commonly made with the patrol control, allowing to simplify the control to the memory unit.
COPYRIGHT: (C)1981,JPO&Japio
JP9528979A 1979-07-26 1979-07-26 Data processor having memory unit Pending JPS5619599A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9528979A JPS5619599A (en) 1979-07-26 1979-07-26 Data processor having memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9528979A JPS5619599A (en) 1979-07-26 1979-07-26 Data processor having memory unit

Publications (1)

Publication Number Publication Date
JPS5619599A true JPS5619599A (en) 1981-02-24

Family

ID=14133609

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9528979A Pending JPS5619599A (en) 1979-07-26 1979-07-26 Data processor having memory unit

Country Status (1)

Country Link
JP (1) JPS5619599A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02157083A (en) * 1988-12-06 1990-06-15 Daiken Iki Kk Treatment of waste liquid including body fluid
WO2008047443A1 (en) 2006-10-20 2008-04-24 Fujitsu Limited Memory device and refresh adjusting method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02157083A (en) * 1988-12-06 1990-06-15 Daiken Iki Kk Treatment of waste liquid including body fluid
JPH0460713B2 (en) * 1988-12-06 1992-09-28 Daiken Iki Kk
WO2008047443A1 (en) 2006-10-20 2008-04-24 Fujitsu Limited Memory device and refresh adjusting method
US8539310B2 (en) 2006-10-20 2013-09-17 Fujitsu Limited Memory device and refresh adjusting method

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