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JPS56154820A - Pulse shaping circuit - Google Patents

Pulse shaping circuit

Info

Publication number
JPS56154820A
JPS56154820A JP5848980A JP5848980A JPS56154820A JP S56154820 A JPS56154820 A JP S56154820A JP 5848980 A JP5848980 A JP 5848980A JP 5848980 A JP5848980 A JP 5848980A JP S56154820 A JPS56154820 A JP S56154820A
Authority
JP
Japan
Prior art keywords
output
circuit
pulse
delay
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5848980A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5848980A priority Critical patent/JPS56154820A/en
Publication of JPS56154820A publication Critical patent/JPS56154820A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE:To obtain a pulse output which is invariably constant in width against fluctuations of an input pulse signal by using three latch circuits and delay circuits. CONSTITUTION:Latch circuit 4 stored with an input signal, latch circuit 6 set by its output, delay circuit 7 which delays its output, and latch circuit 12 which is set by the output of delay circuit 7 and completes pulse generating operation by its output are provided. Until delay circuit 7 generates its output, latch circuit 6 never varies, so AND circuit 9 continues to generate its output. Therefore, even if a pulse less than delay time is inputted, the output is generated for the delay time. In addition, since AND circuit 9 is turned off for the delay time, a pulse output having prescribed width is generated even when a short-width pulse is inputted right after the discontinuance of the input pulse. Two said irregular inputs are detected by irregular signal detecting circuit 119 to send a report on them.
JP5848980A 1980-04-30 1980-04-30 Pulse shaping circuit Pending JPS56154820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5848980A JPS56154820A (en) 1980-04-30 1980-04-30 Pulse shaping circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5848980A JPS56154820A (en) 1980-04-30 1980-04-30 Pulse shaping circuit

Publications (1)

Publication Number Publication Date
JPS56154820A true JPS56154820A (en) 1981-11-30

Family

ID=13085837

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5848980A Pending JPS56154820A (en) 1980-04-30 1980-04-30 Pulse shaping circuit

Country Status (1)

Country Link
JP (1) JPS56154820A (en)

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